Energy-delay efficiency of VLSI computations

GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI

Volumn , Issue , 2002, Pages 104-111

  Pénzes, Paul I ^a   Martin, Alain J ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Energy delay optimization; Transistor sizing

Indexed keywords

DELAY CIRCUITS; ECONOMIC AND SOCIAL EFFECTS; VLSI CIRCUITS;

COMPOSITIONAL PROPERTIES; ENERGY DELAY; ENERGY-DELAY OPTIMIZATION; GLOBAL OPTIMUM; MINIMUM ENERGY; SEQUENTIAL COMPOSITIONS; TRADE OFF; TRANSISTOR SIZING;

ENERGY EFFICIENCY;

EID: 84991935560     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/505306.505330     Document Type: Conference Paper

References (7)

1. Alain J. Martin. Towards an Energy Complexity of Computation. Information Processing Letters, 77, 2001.
2. R. Gonzalez and M. Horowitz. Supply and threshold voltage scaling for low power CMOS. IEEE Journal of Solid-State Circuits, August 1997.
3. Paul I. Pénzes and Alain Martin. Global and Local Properties of Asynchronous Circuits Optimized for Energy Efficiency. IEEE Workshop on Power Management for Real-time and Embedded Systems, Taipei, Taiwan, May 29th, 2001.
4. Alain Martin, Mika Nyström, Paul I. Pénzes. ET2: A Metric for Time and Energy Efficiency of Computation. Power-Aware Computing, Kluwer Academic/Plenum Publishers, 2002
5. Paul I. Pénzes. Energy-delay Efficiency of Asynchronous Circuits, Ph.D. Thesis (in preparation), California Institute of Technology, 2002.
6. José A. Tierno. An Energy-Complexity Model for VLSI Computations, Ph.D. Thesis, California Institute of Technology, 1995.
7. Anantha P. Chandrakasan, Robert W. Brodersen Low Power Digital CMOS Design Kluwer Academic Publishers, 1995