Low power and high speed explicit-pulsed flip-flops

Midwest Symposium on Circuits and Systems

Volumn 2, Issue , 2002, Pages

  Zhao, Peiyi ^a   Darwish, Tarek ^a   Bayoumi, Magdy ^a  

^a University of Louisiana at Lafayette   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; PROBLEM SOLVING; STANDBY POWER SYSTEMS; SWITCHING; TRANSISTORS;

HIGH-SPEED DESIGNS;

FLIP FLOP CIRCUITS;

EID: 0036973622     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. Heo, S., and Asanovic, K.: 'Load-Sensitive Flip-Flop Characterization', IEEE Workshop on VLSI, April 2001, Orlando, Florida, USA, pp. 87-92.
3. Tschanz, J., Narendra, S., Chen, Z.P., Borkar, S., Sachdev, M. and De, V, 'Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors', ISPLED'01, Aug. 2001, Huntington Beach, California, pp. 207-212.
4. Kong, B., Kim, S., and Jun, Y., 'Conditional-capture flip-flop for statistical power reduction', IEEE Journal of Solid-State Circuits, Aug. 2001, 36(8) pp. 1263-1271.
5. Yuan, J., and Svensson, C.: 'High-Speed CMOS Circuit Technique', IEEE Journal of Solid-State Circuits, Feb. 1989, 24 (1), pp.62-70.
6. RABAEY, J.M.: 'Digital Integrated Circuits' (Prentice Hall, New Jersey, 1996 2nd edn.
7. Stojanovic, V., and Oklobdzija, V.G.: 'Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low Power System', IEEE Journal of Solid State Circuits, 1999, 34(4) pp. 536-548.