Load-sensitive flip-flop characterizations

Proceedings - IEEE Computer Society Workshop on VLSI, WVLSI 2001

Volumn , Issue , 2001, Pages 87-92

  Heo, Seongmoo ^a   Asanovic K ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY UTILIZATION;

ELECTRICAL EFFORTS; ELECTRICAL LOAD; FLIP-FLOP DESIGNS; LOAD-SENSITIVE; PARASITIC DELAYS; RELATIVE RANKINGS;

FLIP FLOP CIRCUITS;

EID: 84964502180     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWV.2001.923144     Document Type: Conference Paper

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