Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 166-171

  Zyuban, Victor ^a   Strenski, Philip ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Energy; Energy efficiency; Hardware intensity; Metric; Power

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER CIRCUITS; CONSTRAINT THEORY; MATHEMATICAL MODELS; MICROCOMPUTERS; MICROPROCESSOR CHIPS; OPTIMIZATION;

ARCHITECTURAL COMPLEXITY; HARDWARE INTENSITY;

ELECTRIC POWER SUPPLIES TO APPARATUS;

EID: 0036953966     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2002.146731     Document Type: Conference Paper

References (10)

1. T. Burd and R. Brodersen. Energy efficient CMOS microprocessor design. In Proceedings of the 28th Annual Hawaii International Conference on System Sciences, pages 288-297, 1995.
2. A. Chandrakasan, S. Sheng, and R. Brodersen, Low-power CMOS digital design. IEEE Journal of Solid-State Circuits, 27(4):473-484, April 1992.
3. A. Conn et al. Gradient-based optimization of custom circuits using a static-timing formulation. In Proceedings of Design Automation Conference, pages 452-459, June 1999.
4. R. Gonzalez and M. Horowitz, Energy dissipation in general purpose microprocessors. IEEE Journal of Solid-State Circuits, 31(9):1277-1283, September 1996.
5. P. Penzes and A. Martin, Energy-delay efficiency of VLSI computations. In Proceedings of the Great Lakes Symposium on VLSI, pages 104-107, April 2002.
6. M. Stan, Low-power CMOS with subvolt supply voltages. IEEE Transactions on VLSI Systems, 9(2):394-400, April 2001.
7. J. Veendrick, Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits. IEEE Journal of Solid-State Circuits, 19(4):468-473, August 1984.
8. V. Zyuban, Unified architecture level energy-efficiency metric. In Proceedings of the Great Lakes Symposium on VLSI, pages 24-29, April 2002.
9. V. Zyuban and P. Kogge, Optimization of high-performance superscalar architectures for energy efficiency. In IEEE Symposium on Low Power Electronics and Design, pages 84-89, August 2000.
10. V. Zyuban and D. Meltzer, Clocking strategies and scannable latches for low power applications. In IEEE Symposium on Low Power Electronics and Design, pages 346-351, August 2001.