The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 2002, Pages 14-24

  Hrishikesh, M S ^a   Jouppi, Norman P ^b   Farkas, Keith I ^b   Burger, Doug ^c   Keckler, Stephen W ^c   Shivakumar, Premkishore ^c  

^a Department of Electrical and Computer Engineering ^*  (United States)

^b University of Texas at Austin   (United States)

^c HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DELAY CIRCUITS; ELECTRONIC TIMING DEVICES; INTEGER PROGRAMMING; NANOTECHNOLOGY; NATURAL FREQUENCIES; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS;

SEGMENTED INSTRUCTION WINDOWS;

MICROPROCESSOR CHIPS;

EID: 0036287089     PISSN: 08847495     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCA.2002.1003558     Document Type: Article

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