Conditional techniques for low power consumption flip-flops

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2001, Pages 803-806

  Nedovic, Nikola ^a   Aleksic, Marko ^a   Oklobdzija, Vojin G ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY DELAY PRODUCT; LOW-POWER CONSUMPTION; POWER CONSUMPTION; PRE-CHARGE; VLSI SYSTEM;

FLIP FLOP CIRCUITS;

VLSI CIRCUITS;

EID: 0347976233     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. B. S. Kong, S. S. Kim, Y. H. Jun, "Conditional Capture Flip-Flop Technique for Statistical Power Reduction", Digest of Technical Papers, p290-291, February 2000.
2. N. Nedovic, V. G. Oklobdzija, "Hybrid latch flip-flop with improved power efficiency", Proceedings of SBCCI, p211-215, September 2000.
3. V. Stojanovic, V. G. Oklobdzija, "Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems ", IEEE Journal of Solid-State Circuits, Vol.34, No.4, pp.536-548, April 1999.
4. H. Partovi, et. al., "Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements, " ISSCC Digest of Technical Papers, pp. 132-139, February 1996.