Flow-through latch and edge-triggered flip-flop hybrid elements

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 39, Issue , 1996, Pages 138-139

  Partovi, Hamid ^a   Burd, Robert ^a   Salim, Udin ^a   Weber, Frederick ^a   DiGregorio, Luigi ^a   Draper, Donald ^a  

^a NexGen   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; CLOCKS; COMPUTER SIMULATION; CRITICAL PATH ANALYSIS; DELAY CIRCUITS; HYBRID INTEGRATED CIRCUITS; LOGIC CIRCUITS; LOGIC GATES; PERFORMANCE; TIMING CIRCUITS;

CLOCK LOAD; DYNAMIC DOMINO LOGIC; HYBRID LATCH FLIPFLOP; LATCH LATENCY; SELF RESETTING LOGIC; STATIC LOGIC; TRANSPARENT HIGH LATCH; TRANSPARENT LOW LATCH;

FLIP FLOP CIRCUITS;

EID: 0030083355     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)