Conditional-capture flip-flop for statistical power reduction

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 8, 2001, Pages 1263-1271

  Kong, Bai Sun ^a   Kim, Sam Soo ^b   Jun, Young Hyun ^c  

^a Hankuk Aviation University   (South Korea)

^b Hynix Semiconductor Inc   (South Korea)

^c Sungkyunkwan University   (South Korea)

Author keywords

CMOS digital integrated circuits; Flip flops; Low power; Master slave latches

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; STATISTICAL METHODS; SWITCHING;

STATISTICAL POWER REDUCTION;

FLIP FLOP CIRCUITS;

EID: 0035429510     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.938376     Document Type: Article

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