Analysis and comparison in the energy-delay-area domain of nanometer CMOS Flip-Flops: Part II-results and figures of merit

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 5, 2011, Pages 737-750

  Alioto, Massimo ^a,b   Consoli, Elio ^c   Palumbo, Gaetano ^c  

^a UNIVERSITY OF SIENA   (Italy)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c UNIVERSITY OF CATANIA   (Italy)

Author keywords

Clocking; energy efficiency; energy delay tradeoff; flip flops (FFs); high speed; interconnects; leakage; logical effort; low power; nanometer technologies; VLSI

Indexed keywords

CLOCKING; ENERGY-DELAY TRADEOFF; FLIP-FLOPS (FFS); HIGH SPEED; INTERCONNECTS; LEAKAGE; LOGICAL EFFORT; LOW POWER; NANOMETER TECHNOLOGIES; VLSI;

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; FLIP FLOP CIRCUITS; TOPOLOGY;

ENERGY EFFICIENCY;

EID: 79955567438     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2041377     Document Type: Article

References (35)

1. M. Alioto, E. Consoli, and G. Palumbo, "Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flops: Part I-Methodologies and design strategies," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 5, pp. 725-736, May 2011.
2. D. Markovic, B. Nikolic, and R. Brodersen, "Analysis and design of low-energy flip-flops," in Proc. Int. Symp. Low Power Electron. Des., Aug. 2001, pp. 52-55. (Pubitemid 32806528)
3. D. Markovic, J. Tschanz, and V. De, "Transmission-gate based flipflop," U.S. Patent 6 642 765, Nov. 4, 2003.
4. M. Nogawa and Y. Ohtomo, "A data-transition look-ahead DFF circuit for statistical reduction in power consumption," IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 702-706, May 1998. (Pubitemid 128573475)
5. H. Partovi, R. Burd, U. Salim, F. Weber, L. DiGregorio, and D. Draper, "Flow-through latch and edge-triggered flip-flop hybrid elements," in Proc. IEEE Int. Solid-State Circuit Conf., Feb. 1996, pp. 138-139.
6. F. Klass, C. Amir, A. Das, K. Aingaran, C. Truong, R.Wang, A. Mehta, R. Heald, and G.Yee, "A newfamily of semidynamic and dynamic flipflops with embedded logic for high-performance processors," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 712-716, May 1999.
7. R. Heald, K. Aingaran, C. Amir, M. Ang, M. Boland, P. Dixit, G. Gouldsberry, D. Greenley, J. Grinberg, J. Hart, T. Horel, W. Hsu, J. Kaku, C. Kim, S. Kim, F. Klass, H. Kwan, G. Lauterbach, R. Lo, H. McIntyre, A. Mehta, D. Murata, S. Nguyen, Y. Pai, S. Patel, K. Shin, K. Tam, S. Vishwanthaiah, J. Wu, G. Yee, and E. You, "A third generation SPARC V9 64-b microprocessor," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1526-1538, Nov. 2000. (Pubitemid 32070544)
8. N. Nedovic, "Clocked storage elements for high-performance applications," Ph.D. dissertation, Dept. Elect. Comput. Eng., Univ. California, Davis, 2003.
9. N. Nedovic, M. Aleksic, and V. Oklobdzija, "Conditional techniques for low power consumption flip-flops," in Proc. IEEE Int. Conf. Electron., Circuits Syst., Feb./May 2001, vol. 2, pp. 803-806.
10. P. Zhao, T. Darwish, and M. Bayoumi, "Low power and high speed explicit-pulsed flip-flops," in Proc. IEEE Midw. Symp. Circuits Syst., Aug. 2002, pp. 477-480.
11. S. Naffziger,G. Colon-Bonet, T. Fischer,R. Riedlinger, T. Sullivan, and T. Grutkowski, "The implementation of the itanium 2 microprocessor," IEEE J. Solid-State Circuit, vol. 37, no. 11, pp. 1448-1460, Nov. 2002. (Pubitemid 35432165)
12. B. Nikolic, V. Stojanovic, V. Oklobdzija, W. Jia, J. Chiu, and M. Leung, "Improved sense-amplifier-based flip-flop: Design and measurements," IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 876-884, Jun. 2000.
13. N. Nedovic, V. Oklobdzija, and W. Walker, "A clock skew absorbing flip-flop," in Proc. IEEE Int. Solid-State Circuit Conf., Feb. 2003, pp. 342-344.
14. B. Kong, S. Kim, and Y. Jun, "Conditional-capture flip-flop for statistical power reduction," IEEE J. Solid-State Circuits, vol. 36, no. 8, pp. 1263-1271, Aug. 2001. (Pubitemid 33142045)
15. S. Shin and B. Kong, "Variable sampling window flip-flops for lowpower high-speed VLSI," IEE Proc. IEE Circuits, Devices Syst., vol. 152, no. 3, pp. 266-271, Jun. 2005. (Pubitemid 41119197)
16. R. Llopis and M. Sachdev, "Low power, testable dual edge triggered flip-flops," in Proc. Int. Symp. Low Power Electron. Des., Aug. 1996, pp. 341-345.
17. N. Nedovic, W.Walker, V. Oklobdzija, and M. Aleksic, "A low power simmetrically pulsed dual edge-triggered flip-flop," in Proc. IEEE Eur. Solid-State Circuits Conf., Sep. 2002, pp. 399-402.
18. J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev, and V. De, "Comparative delay and energy of single edge-triggered and dual edgetriggered pulsed flip-flops for high-performance microprocessors," in Proc. Int. Symp. Low Power Electron. Des., Aug. 2001, pp. 147-152. (Pubitemid 32806548)
19. P. Zhao, T. Darwish, and M. Bayoumi, "High-performance and lowpower conditional discharge flip-flop," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 5, pp. 477-484, May 2004.
20. M. Alioto, E. Consoli, and G. Palumbo, "General strategies to design nanometer flip-flops in the energy-delay space," IEEE Trans. Circuits Syst. I, Reg. Papers, to be published.
21. C. Giacomotto, N. Nedovic, and V. Oklobdzija, "The effect of the system specification on the optimal selection of clocked storage elements," IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1392-1404, Jun. 2007. (Pubitemid 46853247)
22. S. Heo and K. Asanovic, "Load-sensitive flip-flop characterization," in Proc. IEEE Comput. Soc. Workshop VLSI, Apr. 2001, pp. 87-92.
23. S. Heo, R. Krashinsky, and K. Asanovic, "Activity-sensitive flip-flop and latch selection for reduced energy," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 9, pp. 1060-1064, Sep. 2007. (Pubitemid 47295159)
24. N. Weste and D. Harris, CMOS VLSI Design: A Circuits and System Perspective (3rd edition). Boston, MA: Addison Wesley, 2004.
25. V. Oklobdzija, V. Stojanovic, D. Markovic, and N. Nedovic, Digital System Clocking: High-Performance and Low-Power Aspects. New York: Wiley-IEEE Press, 2003.
26. H. Partovi, "Clocked storage elements," in Design of High-Performance Microprocessor Circuits. Piscataway, NJ: IEEE Press, 2001, pp. 207-234.
27. V. Stojanovic and V. Oklobdzija, "Comparative analysis of masterslave latches and flip-flops for high-performance and low-power systems," IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 536-548, Apr. 1999.
28. N. Nedovic and V. Oklobdzija, "Dual-edge triggered storage elements and clocking strategy for low-power systems," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 5, pp. 577-590, May 2005. (Pubitemid 40672547)
29. S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Technologies. New York: Springer, 2006.
30. A. Abdollahi, F. Fallah, and M. Pedram, "Leakage current reduction in CMOS VLSI circuits by input vector control," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 2, pp. 140-154, Feb. 2004.
31. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOScircuits," Proc. IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003. (Pubitemid 43779250)
32. M. Agostinelli, M. Alioto, D. Esseni, and L. Selmi, "Leakage-delay tradeoff in FinFET logic circuits: A comparative analysys with bulk technology," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., to be published.
33. P. Gronowski, W. Bowhill, R. Preston, M. Gowan, and R. Allmon, "High-performance microprocessor design," IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 676-686, May 1998.
34. D. Bailey and B. Benschneider, "Clocking design and analysis for a 600-MHz alpha microprocessor," IEEE J. Solid-State Circuits, vol. 33, no. 11, pp. 1627-1633, Nov. 1998. (Pubitemid 128600337)
35. M. Alioto, E. Consoli, and G. Palumbo, "Flip-flop energy/performance versus clock slope and impact on the clock network design," IEEE Trans. Circuits Syst. I, Reg. Papers, to be published.