Clocking and clocked storage elements in a multi-gigahertz environment

IBM Journal of Research and Development

Volumn 47, Issue 5-6, 2003, Pages 567-583

  Oklobdzija, Vojin G ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFICATION; CAPACITANCE; DATA TRANSFER; DIGITAL STORAGE; ELECTRIC CONDUCTIVITY; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; STANDBY POWER SYSTEMS;

CLOCK FREQUENCIES; CLOCKED STORAGE ELEMENTS;

TIMING CIRCUITS;

EID: 0346267659     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.475.0567     Document Type: Article

References (39)

1. S. Borkar, "Design Challenges of Technology Scaling," IEEE Micro 19, No. 4, 23-29 (August 1999).
2. P. E. Gronowski, W. J. Bowhill, R. P. Preston, M. K. Gowan, and R. L. Allmon, "High-Performance Microprocessor Design," IEEE J. Solid-State Circuits 33, No. 5, 676-686 (May 1998).
3. E. G. Friedman, Ed., Clock Distribution Networks in VLSI Circuits and Systems, IEEE Press, Piscataway, NJ, 1995.
4. V. G. Oklobdzija, Ed., High-Performance System Design: Circuits and Logic, IEEE Press, Piscataway, NJ, 1999.
5. D. W. Bailey and B. J. Benschneider, "Clocking Design and Analysis for a 600-MHz Alpha Microprocessor," IEEE J. Solid-State Circuits 33, No. 11, 1627-1633 (November 1998).
6. J. Schutz and R. Wallace, "A 450MHz IA32 P6 Family Microprocessor," Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, February 1998, pp. 236-237.
7. W. P. Burleson, M. Ciesielski, F. Klass, and W. Liu, "Wave-Pipelining: A Tutorial and Research Survey," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 6, No. 3, 464-474 (September 1998).
8. D. Harris and M. A. Horowitz, "Skew-Tolerant Domino Circuits," IEEE J. Solid-State Circuits 32, No. 11, 1702-1711 (November 1997).
9. D. Harris, Skew-Tolerant Circuit Design, Morgan Kaufmann Publishers, San Francisco, 2001.
10. L. W. Gotten, "Circuit Implementation of High-Speed Pipeline Systems," Proceedings of the Fall Joint Computer Conference (AFIPS), 1965, pp. 489-504.
11. IBM Corporation, LSSD Rules and Applications, Manual 3531, Release 59.0, March 29, 1985.
12. G. Gerosa, S. Gary, C. Dietz, D. Pham, K. Hoover, J. Alvarez, H. Sanchez, P. Ippolito, T. Ngo, S. Litch, J. Eno, J. Golab, N. Vanderschaaf, and J. Kahle, "A 2.2 W, 80 MHz Superscalar RISC Microprocessor," IEEE J. Solid-State Circuits 29, No. 12, 1440-1452 (December 1994).
13. D. W. Dobberpuhl, "Circuits and Technology for Digital's StrongARM and ALPHA Microprocessors," Proceedings of the 17th Conference on Advanced Research in VLSI, 1997, pp. 2-11.
14. W. C. Madden and W. J. Bowhill, "High Input Impedance, Strobed Sense-Amplifier," U.S. Patent 4,910,713, March 1990.
15. B. Nikolic and V. G. Oklobdzija, "Design and Optimization of Sense-Amplifier-Based Flip-Flops," Proceedings of the 25th European Solid-State Circuits Conference (ESSCIRC'99), 1999, pp. 410-413.
16. V. Stojanovic and V. G. Oklobdzija, "Flip-Flop," U.S. Patent 6,232,810, May 2001.
17. B. Nikolic, V. G. Oklobdzija, V. Stojanovic, W. Jia, J. Chiu, and M. Leung, "Improved Sense-Amplifier-Based Flip-Flop: Design and Measurements," IEEE J. Solid-State Circuits 35, No. 6, 876-884 (June 2000).
18. B. Nikolic, V. Stojanovic, V. G. Oklobdzija, W. Jia, J. Chiu, and M. Leung, "Sense Amplifier Based Flip-Flop," Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, 1999, pp. 282-283.
19. H. Partovi, R. Burd, U. Salim, F. Weber, L. DiGregorio, and D. Draper, "Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements," Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, 1996, pp. 138-139.
20. F. Klass, "Semi-Dynamic and Dynamic Flip-Flops with Embedded Logic," Proceedings of the Symposium on VLSI Circuits, Digest of Technical Papers, 1998, pp. 108-109.
21. N. Nedovic and V. G. Oklobdzija, "Dynamic Flip-Flop with Improved Power," Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'00), 2000, pp. 323-326.
22. J. Tschanz James, S. Narendra, Z. Chen, S. Borkar, M. Sachdev, and V. De, "Comparative Delay and Energy of Single Edge-Triggered and Dual Edge-Triggered Pulsed Flip-Flops for High-Performance Microprocessors," Proceedings of the International Symposium on Low Power Electronics and Design, 2001, pp. 147-152.
23. S. H. Unger and C.-J. Tan, "Clocking Schemes for High-Speed Digital Systems," IEEE Trans. Computers C-35, No. 10, 880-895 (October 1986).
24. V. Stojanovic and V. G. Oklobdzija, "Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power VLSI Systems," IEEE J. Solid-State Circuits 34, No. 4, 536-548 (April 1999).
25. V. G. Oklobdzija, V. Stojanovic, D. Markovic, and N. Nedovic, Digital System Clocking: High-Performance and Low-Power Aspects, John Wiley & Sons, Inc., Hoboken, NJ, 2003.
26. M. Horowitz, T. Indermaur, and R. Gonzalez, "Low-Power Digital Design," Proceedings of the IEEE Symposium on Low-Power Electronics, 1994, pp. 8-11.
27. V. Zyuban and P. Strenski, "Unified Methodology for Resolving Power-Performance Tradeoffs at the Microarchitectural and Circuit Level," Proceedings of the International Symposium on Low-Power Electronics and Design, 2002, pp. 166-171.
28. T. Kuroda and T. Sakurai, "Overview of Low-Power ULSI Circuit Techniques," IEICE Trans. Electron. E78-C, No. 4, 334-344 (April 1995).
29. B. S. Kong, S. S. Kim, and Y. H. Jun, "Conditional Capture Flip-Flop Technique for Statistical Power Reduction," Proceedings of the IEEE International SolidState Circuits Conference (ISSCC), Digest of Technical Papers, 2000, pp. 290-291.
30. N. Nedovic, M. Aleksic, and V. G. Oklobdzija, "Conditional Techniques for Small Power Consumption Flip-Flops," Proceedings of the 8th IEEE International Conference on Electronics, Circuits and Systems, 2001, pp. 803-806.
31. N. Nedovic, M. Aleksic, and V. G. Oklobdzija, "Conditional Pre-Charge Techniques for Power-Efficient Dual-Edge Clocking," Proceedings of the International Symposium on Low-Power Electronics and Design, 2002, pp. 56-59.
32. M. Saint-Laurent, V. G. Oklobdzija, S. S. Singh, and M. Swaminathan, "Optimal Sequencing Energy Allocation for CMOS Integrated Systems," Proceedings of the International Symposium on Quality Electronic Design, 2002, pp. 94-99.
33. N. Nedovic, W. W. Walker, V. G. Oklobdzija, and M. Aleksic, "A Low Power Symmetrically Pulsed Dual Edge-Triggered Flip-Flop," Proceedings of Ihe European Solid-State Circuits Conference (ESSCIRC'02), 2002, pp. 399-402.
34. N. Nedovic and V. G. Oklobdzija, "Hybrid Latch Flip-Flop with Improved Power Efficiency," Proceedings of the 13th Symposium on Integrated Circuits and Systems Design (SBCCI'00), 2000, pp. 211-215.
35. Y. Suzuki, K. Odagawa, and T. Abe, "Clocked CMOS Calculator Circuitry," IEEE J. Solid-State Circuits 8, No. 6, 462-469 (December 1973).
36. J. Yuan and C. Svensson, "New Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings," IEEE J. Solid-State Circuits 32, No. 1, 62-69 (January 1997).
37. F. Klass, C. Amir, A. Das, K. Aingaran, C. Truong, R. Wang, A. Mehta, R. Heald, and G. Yee, "A New Family of Semidynamic and Dynamic Flip-Flops with Embedded Logic for High-Performance Processors," IEEE J. Solid-State Circuits 34, No. 5, 712-716 (May 1999).
38. J. Montanaro, R. T. Witek, K. Anne, A. J. Black, E. M. Cooper, D. W. Dobberpuhl, P. M. Donahue, J. Eno, W. Hoeppner, D. Kruckemyer, T. H. Lee, P. C. M. Lin, L. Madden, D. Murray, M. H. Pearce, S. Santhanam, K. J. Snyder, R. Stehpany, and S. C. Thierauf, "A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor," IEEE J. Solid-State Circuits 31, No. 11, 1703-1714 (November 1996).
39. A. G. M. Strollo, E. Napoli, and C. Cimino, "Low Power Double Edge-Triggered Flip-Flop Using One Latch," IEE Electron. Lett. 35, No. 3, 187-188 (February 1999).