Supply and threshold voltage scaling for low power CMOS

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 8, 1997, Pages 1210-1216

  Gonzalez, Ricardo ^a,c   Gordon, Benjamin M ^{a,b,c,d,e,f,g}   Horowitz, Mark A ^a,c,e,h,i  

^a STANFORD UNIVERSITY   (United States)

^b University of Washington   (United States)

^c Stanford University ^*

^d Applied Research Laboratory   (United States)

^e MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^f University of Washington   (United States)

^g UNIVERSITY OF WASHINGTON   (United States)

^h Dept of of Electrical Engineering ^*  (United States)

ⁱ RAMBUS INC   (United States)

Author keywords

Energy delay product; Low power CMOS circuits; Threshold scaling

Indexed keywords

DELAY CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK PARAMETERS; ENERGY EFFICIENCY; FEEDBACK CONTROL; TRANSISTORS;

THRESHOLD VOLTAGE SCALING;

CMOS INTEGRATED CIRCUITS;

EID: 0031212817     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.604077     Document Type: Article

References (15)

1. J. B. Burr, "Cryogenic ultra low power CMOS," in IEEE Int. Symp. Low Power Electronics, 1995, p. 9.4.
2. J. B. Burr and A. M. Peterson, "Ultra low power CMOS technology," in NASA VLSI Design Symp., 1991, pp. 4.2.1-4.2.13.
3. A. Chatterjee, M. Nandakumar, and I. Chen, "An investigation of the impact of technology scaling on power wasted as short current in low voltage CMOS," in IEEE Int. Symp. Low Power Electronics and Design, Aug. 1996, pp. 145-150.
4. D. Dobberphul, Personal communication.
5. V. Kaenel, D. Aebischer, C. Piquet, and E. Dijkstra, "A 320 MHz 1.5 mW at 1.35 V CMOS PLL for microprocessor clock generation," in IEEE Int. Solid-State Circuits Conf., Feb. 1996, pp. 132-133.
6. 2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme," in IEEE Int. Solid-State Circuits Conf., Feb. 1996, pp. 166-167.
7. J. Montanaro, R. T. Witek, et al., "A 160 MHz 32 b 0.5 W CMOS RISC microprocessor," in IEEE Int. Solid-State Circuits Conf., Feb. 1996, pp. 215-215.
8. S. Mutoh, S. Shigematsu, Y. Matsuya, et al., "A 1 V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone applications," in IEEE Int. Solid-State Circuits Conf., Feb. 1996, vol. 39, pp. 168-169.
9. M. Nandakumar, A. Chatterjee, M. Rodder, et al., "A device design study of 0.25 μm gate length CMOS for 1 V low power applications," in IEEE Int. Symp. Low Power Electronics, Oct. 1995, pp. 80-81.
10. T. Sakurai and A. R. Newton, "Alpha-power law MOSFET model and its application to CMOS inverter delay and other formulas," IEEE J. Solid-State Circuits, vol. 25, pp. 584-593, Apr. 1990.
11. K. Seta, H. Hara, T. Kuroda, et al, "50% active-power saving without speed degradation using standby power reduction (SPR) circuit," in IEEE Int. Solid-State Circuits Conf., Feb. 1995, vol. 38, pp. 318-319.
12. R. R. Troutman. "Drain-induced barrier lowering," IEEE J. Solid-State Circuits, vol. 14, p. 383, Apr. 1979.
13. H. Veendrick, "Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits," IEEE J. Solid-State Circuits, vol. 19, pp. 468-473, Aug. 1984.
14. C. Vieri, I. Yang, A. Chandrakasan, et al., "SOIAS: dynamically variable threshold SOI with active substrate," in IEEE Int. Symp. Low Power Electronics, Oct. 1995, pp. 86-87.
15. G.-Y. Wei and M. Horowitz, "A low power switching power supply for self-clocked systems," in IEEE Int. Symp. Low Power Electronics and Design, Aug. 1996, pp. 313-317.