High-performance and low-power conditional discharge flip-flop

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 5, 2004, Pages 477-484

  Zhao, Peiyi ^a   Darwish, Tarek K ^a   Bayoumi, Magdy A ^a  

^a University of Louisiana at Lafayette   (United States)

Author keywords

Digital CMOS; Flip flop; Low power; Very large scale integration (VLSI)

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; ELECTRIC DISCHARGES; ENERGY UTILIZATION; ROUTERS; SWITCHING; VLSI CIRCUITS;

D-TO-Q DELAY; DIGITAL CMOS; HYBRID LATCH FLIP-FLOP (HLFF); LOW POWERS;

FLIP FLOP CIRCUITS;

EID: 2542507417     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.826192     Document Type: Article

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