Parasitic capacitances: Analytical models and impact on circuit-level performance

IEEE Transactions on Electron Devices

Volumn 58, Issue 5, 2011, Pages 1361-1370

  Wei, Lan ^a,b   Boeuf, Frédéric ^c   Skotnicki, Thomas ^c   Wong, H S Philip ^a  

^a Stanford University   (United States)

^b Massachusetts Institute of Technology Cambridge   (United States)

^c STMICROELECTRONICS   (France)

Author keywords

Bulk; circuit level performance; complementary metaloxidesemiconductor (CMOS); double gate (DG); fully depleted silicon on insulator (FDSOI); parasitic capacitances

Indexed keywords

BULK; CIRCUIT-LEVEL PERFORMANCE; COMPLEMENTARY METALOXIDESEMICONDUCTOR (CMOS); DOUBLE GATE; FULLY DEPLETED SILICON-ON-INSULATOR; PARASITIC CAPACITANCE;

COMPUTER SIMULATION; MATHEMATICAL MODELS; MODELS;

CAPACITANCE;

EID: 79955543198     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2121912     Document Type: Article

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