An advanced low power, high performance, strained channel 65nm technology

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2005, Issue , 2005, Pages 245-247

  Tyagi, S ^a   Auth, C ^a   Bai, P ^a   Curello, G ^a   Deshpande, H ^a   Gamavaram, S ^a   Golonzka, O ^a   Heussner, R ^a   James, R ^a   Kenyon, C ^a   Lee, S H ^a   Lindert, N ^a   Liu, M ^a   Nagisetty, R ^a   Natarajan, S ^a   Parker, C ^a   Sebastian, J ^a   Sell, B ^a   Sivakumar, S ^a   St Amour, A ^a   Tone, K ^a   more..

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; ELECTRIC LINES; ELECTRONICS INDUSTRY; FIELD EFFECT TRANSISTORS; STRAIN;

NMOS; PMOS; STRAINED CHANNELS;

CMOS INTEGRATED CIRCUITS;

EID: 33847757850     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iedm.2005.1609318     Document Type: Conference Paper

References (2)

1. P. Bai., IEDM Tech. Dig., p. 197-200, 2004
2. K. Mistry, VLSI Symp Dig, p. 50-51, 2004