A 45nm low power system-on-chip technology with dual gate (Logic and I/O) high-k/ metal gate strained silicon transistors

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Jan, C H ^a   Bai, P ^a   Biswas, S ^a   Buehler, M ^a   Chen, Z P ^a   Curello, G ^a   Gannavaram, S ^a   Hafez, W ^a   He, J ^a   Hicks, J ^a   Jalan, U ^a   Lazo, N ^a   Lin, J ^a   Lindert, N ^a   Litteken, C ^a   Jones, M ^a   Kang, M ^a   Komeyli, K ^a   Mezhiba, A ^a   Naskar, S ^a   Olson, S ^a   Park, J ^a   Parker, R ^a   Pei, L ^a   Post, I ^a   Pradhan, N ^a   Prasad, C ^a   Prince, M ^a   Rizk, J ^a   Sacks, G ^a   Tashiro, H ^a   Towner, D ^a   Tsai, C ^a   Wang, Y ^a   Yang, L ^a   Yeh, J Y ^a   Yip, J ^a   Mistry, K ^a   more..

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BULK CMOS; CMOS SYSTEMS; DUAL GATES; HIGH DENSITIES; LEADING EDGES; LINEAR RESISTORS; LOW-POWER PRODUCTS; LOW-POWER SYSTEMS; METAL GATE TRANSISTORS; METAL GATES; MIM CAPACITORS; OFF-STATE LEAKAGES; OTP FUSE; RF CIRCUITS; RF PERFORMANCE; ROBUST RELIABILITIES; STRAINED SILICONS; TRANSISTOR DRIVE CURRENTS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; ELECTRON DEVICES; HAFNIUM; INTEGRATED CIRCUITS; MIM DEVICES; PROGRAMMABLE LOGIC CONTROLLERS; SEMICONDUCTING SILICON COMPOUNDS; SWITCHING CIRCUITS;

TRANSISTORS;

EID: 64549136597     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796772     Document Type: Conference Paper

References (4)

1. K. Mistry et al, IEDM Tech. Dig., pp. 247-250, 2007
2. C. Auth et al, VLSI Sym. Proc., pp. 128-129, 2008
3. C.-H. Jan et al, IEDM Tech. Dig., pp. 65-68, 2005
4. S. Tyagi et al, IEDM Tech. Dig., pp. 1070-1072, 2005