The impact of device footprint scaling on high-performance CMOS logic technology

IEEE Transactions on Electron Devices

Volumn 54, Issue 5, 2007, Pages 1148-1155

  Deng, Jie ^a   Kim, Keunwoo ^b   Chuang, Ching Te ^b   Wong, H S Philip ^a  

^a Stanford University   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

CMOS; Device footprint; Device scaling; Device variation; Numerical simulation; Selective scaling; Ultrathin body (UTB) fully depleted silicon on insulator (FD SOI)

Indexed keywords

COMPUTER SIMULATION; COUNTING TUBES; ELECTRON MULTIPLIERS; LOGIC DEVICES; NUMERICAL ANALYSIS; SILICON ON INSULATOR TECHNOLOGY;

DEVICE FOOTPRINT; FOOTPRINT SCALING; SELECTIVE SCALING; VARIABILITY ANALYSIS;

CMOS INTEGRATED CIRCUITS;

EID: 34247863681     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.894596     Document Type: Article

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