45nm high-k + metal gate strain-enhanced transistors

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2008, Pages 128-129

  Auth, C ^a   Cappellani, A ^a   Chun, J S ^a   Dalis, A ^a   Davis, A ^a   Ghani, T ^a   Glass, G ^a   Glassman, T ^a   Harper, M ^a   Hattendorf, M ^a   Hentges, P ^a   Jaloviar, S ^a   Joshi, S ^a   Klaus, J ^a   Kuhn, K ^a   Lavric, D ^a   Lu, M ^a   Mariappan, H ^a   Mistry, K ^a   Norris, B ^a   Rahhal orabi, N ^a   Ranade, P ^a   Sandford, J ^a   Shifren, L ^a,b   Souw, V ^a   Tone, K ^a   Tambwe, F ^a   Thompson, A ^a   Towner, D ^a   Troeger, T ^a   Vandervoorn, P ^a   Wallace, C ^a   Wiedemer, J ^a   Wiegand, C ^a   more..

^a Logic Technology Development   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATE DIELECTRICS; GATES (TRANSISTOR); LITHOGRAPHY; TECHNOLOGY; TRANSISTORS;

45 NM TECHNOLOGY; CMOS TRANSISTORS; DRY LITHOGRAPHY; ENHANCEMENT TECHNIQUES; HIGH-K GATE DIELECTRICS; METAL GATES; TRANSISTOR PERFORMANCE; VLSI TECHNOLOGIES;

METALS;

EID: 51949090508     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2008.4588589     Document Type: Conference Paper

References (6)

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4. S. Tyagi, et al, IEDM Tech. Dig. pp 1070-1072, 2005
5. A. Wei, et al, VLSI Sym. Tech. Dig. pp 216-217, 2007
6. C. Kang, et al, IEDM Tech. Dig. pp885-888, 2006