Modeling and optimization of fringe capacitance of nanoscale DGMOS devices

IEEE Transactions on Electron Devices

Volumn 52, Issue 2, 2005, Pages 256-262

  Bansal, Aditya ^a   Paul, Bipul C ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

Conformal mapping; Double gate MOSFET; Fringe capacitance; Gate underlap

Indexed keywords

CAPACITANCE; CONFORMAL MAPPING; ELECTRODES; MATHEMATICAL MODELS; NANOTECHNOLOGY; OPTIMIZATION; OSCILLATORS (ELECTRONIC);

DOUBLE GATE MOSFET; FRINGE CAPACITANCE; GATE UNDERLAP; RING OSCILLATOR;

MOSFET DEVICES;

EID: 13344270339     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.842713     Document Type: Article

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