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Volumn 2005, Issue , 2005, Pages 56-59

High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL

(79)  Lee, W H a   Waite, A a   Nii, H a   Nayfeh, H M a   McGahay, V a   Nakayama, H a   Fried, D a   Chen, H a   Black, L a   Bolam, R a   Cheng, J a   Chidambarrao, D a   Christiansen, C a   Cullinan Scholl, M a   Davies, D R a   Domenicucci, A a   Fisher, P a   Fitzsimmons, J a   Gill, J a   Gribelyuk, M a   more..


Author keywords

[No Author keywords available]

Indexed keywords

DUAL STRESS LINERS (DSL); INTERCONNECT DELAY; STRESS MEMORIZATION TECHNIQUES; TRANSISTOR STRAIN;

EID: 33847739343     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (32)

References (4)
  • 2
    • 33847701943 scopus 로고    scopus 로고
    • H. S. Yang et al. IEDM 2004, p. 1075
    • (2004) IEDM , pp. 1075
    • Yang, H.S.1
  • 3
    • 33847711651 scopus 로고    scopus 로고
    • IITC
    • M. Fukasawa et al., IITC 2005
    • (2005)
    • Fukasawa, M.1
  • 4
    • 4544238135 scopus 로고    scopus 로고
    • K. Rim et al. IEDM 2002 p. 43-46
    • (2002) IEDM , pp. 43-46
    • Rim, K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.