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Volumn 2005, Issue , 2005, Pages 56-59
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High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
a
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Author keywords
[No Author keywords available]
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Indexed keywords
DUAL STRESS LINERS (DSL);
INTERCONNECT DELAY;
STRESS MEMORIZATION TECHNIQUES;
TRANSISTOR STRAIN;
CMOS INTEGRATED CIRCUITS;
DIELECTRIC DEVICES;
ELECTRIC CURRENTS;
FIELD EFFECT TRANSISTORS;
SILICON ON INSULATOR TECHNOLOGY;
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EID: 33847739343
PISSN: 01631918
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (32)
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References (4)
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