Modeling of MOSFET parasitic capacitances, and their impact on circuit performance

Solid-State Electronics

Volumn 51, Issue 11-12, 2007, Pages 1485-1493

  Mueller, Judith ^a   Thoma, Rainer ^a   Demircan, Ertugrul ^a   Bernicot, Christophe ^b   Juge, Andre ^b  

^a FREESCALE SEMICONDUCTOR INC   (United States)

^b STMICROELECTRONICS   (France)

Author keywords

Circuit simulations; Compact modeling; Extrinsic capacitance; MOSFET

Indexed keywords

CIRCUIT SIMULATION; MATHEMATICAL MODELS; MOSFET DEVICES; THREE DIMENSIONAL;

COMPACT MODELING; DESIGN FLOW; EXTRINSIC CAPACITANCE; RING OSCILLATOR MEASUREMENTS;

CAPACITANCE;

EID: 36249015412     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2007.09.025     Document Type: Article

References (8)

1. Mueller J, Caruyer G, Thoma R, Bernicot C, Juge A. Extrinisic, parasitic capacitance contributions of MOSFETs, their impact on performance, and their modeling. In: Proceedings of the 36th European solid-state device research conference; 2006. p. 323-6.
2. Taur Y., and Ning T.H. Fundamentals of VLSI devices (1998), Cambridge University Press p. 224-89
3. ITRS Roadmap, Semiconductor Industry Association. .
4. Sudhama C, Spulber O, McAndrew C, Thoma R. Numerical simulation and analytical modeling of strong-inversion gate capacitance in ultra-short (30 nm) MOSFETs. In: Proceedings of the international conference on modeling and simulation of microsystems, Nanotech 2001, Nov 2001, p. 450-3.
5. Suzuki K. Parasitic capacitance of submicrometer MOSFET's. IEEE Trans Electron Dev 46 (1999) 1895-1900
6. Predaldiny F., Lallement Ch., and Mathiot D. A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs. Solid-state Electron 46 12 (2002) 2191-2198
7. Mohapatra N.R., et al. Modeling of parasitic capacitances in deep submicrometer conventional and high-k dielectric MOS transistors. IEEE Trans Electron Dev 50 4 (2003) 959-966
8. van Dort M.J., Woerlee P.H., and Walker A.J. A simple model for quantisation effects in heavily doped silicon MOSFETs at inversion conditions. Solid-State Electron 37 3 (1994) 411-414