CMOS gate height scaling

International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Volumn , Issue , 2008, Pages 41-42

  Ren, Zhibin ^a   Schonenberg, K T ^b   Ontalus, V ^a   Lauer, I ^b   Butt, S A ^a  

^a IBM RESEARCH   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

45NM NODES; CMOS GATES; CMOS TECHNOLOGIES; GATE ELECTRODES; HEIGHT REDUCTIONS; PERFORMANCE ENHANCEMENTS; PERFORMANCE IMPACTS; RING OSCILLATORS; STRESS LINERS;

CAPACITANCE; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUITS;

GRAIN SIZE AND SHAPE;

EID: 60749099465     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSICT.2008.4734471     Document Type: Conference Paper

References (3)

1. K. Uejima, etal., IEDM, p.493, 2007.
2. A. Majumdar et al., EDL, p. 515, 2008.
3. H. S. Yang et al., IEDM, p. 1075, 2004.