32nm gate-first high-k/metal-gate technology for high performance low power Applications

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Diaz, C H ^a   Goto, K ^a   Huang, H T ^a   Yasuda, Yuri ^a   Tsao, C P ^a   Chu, T T ^a   Lu, W T ^a   Chang, Vincent ^a   Hou, Y T ^a   Chao, Y S ^a   Hsu, P F ^a   Chen, C L ^a   Lin, K C ^a   Ng, J A ^a   Yang, W C ^a   Chen, C H ^a   Peng, Y H ^a   Chen, C J ^a   Chen, C C ^a   Yu, M H ^a   Yeh, L Y ^a   You, K S ^a   Chen, K S ^a   Thei, K B ^a   Lee, C H ^a   Yang, S H ^a   Cheng, J Y ^a   Huang, K T ^a   Liaw, J J ^a   Ku, Y ^a   Jang, S M ^a   Chuang, H ^a   Liang, M S ^a   more..

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

193NM IMMERSION LITHOGRAPHIES; DESIGN RULES; DRIVE CURRENTS; GATE LENGTHS; GATE TECHNOLOGIES; HIGH DRIVE CURRENTS; HIGH-NA; LOW-POWER APPLICATIONS; SRAM CELLS; SUB-THRESHOLD LEAKAGES; TEST CHIPS; ULTRA-HIGH DENSITIES;

ELECTRON DEVICES;

STATIC RANDOM ACCESS STORAGE;

EID: 64549118580     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796770     Document Type: Conference Paper

References (6)

1. K. Mistry et al., "A 45nm logic technology with HK+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging," IEDM Tech. Dig., pp. 247-250, 2007.
2. S. Mayuzumi et al., "Extreme high-performance n and p-MOSFETs boosted by dual-metal/high-k gate damascene process using top-cut dual stress liners on (100) substrates," IEDM Tech. Dig., pp. 293-296, 2007.
3. X. Chen et al., "A cost-effective 32nm High-K metal-gate CMOS technology for low-power applications with single-metal/gate-first process," VLSI Tech. Symp., pp. 88-89, 2008.
4. H.T. Huang et al., "45nm high-k/metal gate CMOS technology for GPU/NPU applications with highest pFET performance," IEDM Tech. Dig., pp. 285-288, 2007.
5. K. L. Cheng et al., "A highly scaled, high performance 45nm bulk logic CMOS technology with 0.242um2 SRAM cell," IEDM Tech. Dig., pp. 243-246, 2007.
6. S. Y. Wu. et al., "A 32nm CMOS low power SoC platform technology for foundry applications with functional high density SRAM," IEDM Tech Dig., pp. 263-266, 2007.