Selective device structure scaling and parasitics engineering: A way to extend the technology roadmap

IEEE Transactions on Electron Devices

Volumn 56, Issue 2, 2009, Pages 312-320

  Wei, Lan ^a   Deng, Jie ^b   Chang, Li Wen ^a   Kim, Keunwoo ^c   Chuang, Ching Te ^d   Wong, H S Philip ^a  

^a Stanford University   (United States)

^b IBM   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

^d NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

CMOS; Contacted gate pitch; Device geometry; Device scaling; Footprint; Parasitic

Indexed keywords

CAPACITANCE; IMPACT RESISTANCE; INDUSTRIAL MANAGEMENT; TECHNOLOGICAL FORECASTING;

CMOS; CONTACTED GATE PITCH; DEVICE GEOMETRY; DEVICE SCALING; FOOTPRINT; PARASITIC;

TECHNOLOGY;

EID: 59849093541     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.2010573     Document Type: Article

References (25)

1. K. Mistry et al., "A 45 nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging," in IEDM Tech. Dig., Washington DC, Dec. 10-12, 2007, pp. 247-250.
2. S. E. Thompson and S. Parthasarathy, "Moore's law: The future of Si microelectronics," Mater. Today, vol. 9, no. 6, pp. 20-25, Jun. 2006.
3. J. W. Sleight, I. Lauer, O. Dokumaci, D. M. Fried, D. Guo, B. Haran, S. Narasimha, C. Sheraw, D. Singh, M. Steigerwalt, X. Wang, P. Oldiges, D. Sadana, C. Y. Sung, W. Haensch, and M. Khare, "Challenges and opportunities for high performance 32 nm CMOS technology," in IEDM Tech. Dig., San Francisco, CA, Dec. 11-13, 2006, pp. 697-700.
4. J. Mueller, R. Thoma, E. Demircan, C. Bermicot, and A. Juge, "Modeling of MOSFET parasitic capacitances, and their impact on circuit performance," Solid State Electron., vol. 51, no. 11/12, pp. 1485-1493, Nov./Dec. 2007.
5. J. Deng, K. Kim, C.-T. Chuang, and H.-S. P. Wong, "The impact of device footprint scaling on high-performance CMOS logic technology," IEEE Trans. Electron Devices, vol. 54, no. 5, pp. 1148-1155, May 2007.
6. ITRS Roadmap. [Online]. Available: http://itrs.net/reports.html
7. C. T. Black, K. W. Guarini, R. Ruiz, E. M. Sikorski, I. V. Babich, R. L. Sandstrom, and Y. Zhang, "Polymer self assembly in semiconductor microelectronics," in IEDM Tech. Dig., San Francisco, CA, Dec. 11-13, 2006, pp. 439-442.
8. L.-W. Chang and H.-S. P. Wong, "Diblock copolymer directed self-assembly for CMOS device fabrication," in Proc. 31st SPIE Int. Symp. Microlithography, Des. Process Integr. Microelectron. Manuf. IV A. A. K. Wong and V. K. Singh, Eds, 2006, vol. 6150, pp. 329-334.
9. J. Bang, S. H. Kim, E. Drockenmuller, M. J. Misner, T. P. Russell, and C. J. Hawker, "Defect-free nanoporous thin films from ABC triblock copolymers," J. Amer. Chem. Soc., vol. 128, no. 23, pp. 7622-7629, May 2006.
10. Maxwell 3D, Pittsburgh, PA: Ansoft Corp.
11. J. Deng and H.-S. P. Wong, "Modeling and analysis of planar gate electrostatic capacitance for 1-D FET with multiple cylindrical conducting channels," IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2377-2385, Sep. 2007.
12. S.-D. Kim, C.-M. Park, and J. C. S. Woo, "Advanced model and analysis of series resistance for CMOS scaling into nanometer regime. I. Theoretical derivation," IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 457-466, Mar. 2002.
13. H. H. Berger, "Contact resistance and contact resistivity," J. Electrochem. Soc., vol. 119, no. 4, pp. 507-514, Apr. 1972.
14. Taurus-Device, Santa Clara, CA: Synopsys Corp., Version 2005.10.
15. S. Thompson, G. Sun, K. Wu, J. Lim, and T. Nishida, "Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs," in IEDM Tech. Dig., San Francisco, CA, Dec. 13-15, 2004, pp. 221-224.
16. N. Shah, "Stress Modelling of Nanoscle MOSFET," M.S. thesis, Univ. Florida, Gainesville, FL, 2005.
17. R. Shenoy and K. Saraswat, "Optimization of extrinsic source/drain resistance in ultrathin body double-gate FETs," IEEE Trans. Nanotechnol., vol. 2, no. 4, pp. 265-270, Dec. 2003.
18. A. Yagishita, T.-J. King, and J. Bokor, "Schottky barrier height reduction and drive current improvement in metal source/drain MOSFET with strained-Si channel," Jpn. J. Appl. Phys., vol. 43, no. 4B, pp. 1713-1716, 2004.
19. A. Kinoshita, C. Tanaka, K. Uchida, and J. Koga, "High-performance 50-nm-gate-length Schottky-source/drain MOSFETs with dopant-segregation junctions," in VLSI Symp. Tech. Dig., Jun. 14-16, 2005, pp. 158-159.
20. D. Connelly, C. Faulkner, D. Grupp, and J. Harris, "A new route to zero-barrier metal source/drain MOSFETs," IEEE Trans. Nanotechnol. vol. 3, no. 1, pp. 98-104, Mar. 2004.
21. T. Takahashi, T. Nishimura, L. Chen, S. Sakata, K. Kita, and A. Toriumi, "Proof of Ge-interfacing concepts for metal/high-k/Ge CMOS," in IEDM Tech. Dig., Washington DC, Dec. 10-12, 2007, pp. 697-700.
22. M. Kobayashi, A. Kinoshita, K. Saraswat, H.-S. P. Wong, and Y. Nishi, "Fermi-level depinning in metal/Ge Schottky junction and its application to metal source/drain Ge NMOSFET," in Proc. VLSI Symp. Technol., Honolulu, HI, Jun. 17-20, 2008, pp. 54-55.
23. J. Hu, D. Choi, J. S. Harris, K. Saraswat, and H.-S. P. Wong, "Fermi-level depinning of GaAs for Ohmic contacts," in Proc. Device Res. Conf., Santa Barbara, CA, Jun. 23-25, 2008.
24. J. Park and C. Hu, "Air spacer MOSFET technology for 20 nm node and beyond," presented at the The 9th Int. Conf. on Solid-State and Integrated-Circuit Technology ICSICT, Beijing, China, Oct. 20-23, 2008, Paper A1.10.
25. Z. Ren, K. T. Schonenberg, V. Ontalus, I. Lauer, and S. A. Butt, "CMOS gate height scaling," in The 9th Int. Conf. on Solid-State and Integrated-Circuit Technology ICSICT, Beijing, China, Oct. 20-23, 2008.