Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Henson, K ^a   Bu, H ^a   Na, M H ^a   Liang, Y ^a   Kwon, U ^a   Krishnan, S ^a   Schaeffer, J ^b   Jha, R ^a   Moumen, N ^a   Carter, R ^c   De Wan, C ^a   Donaton, R ^a   Guo, D ^a   Hargrove, M ^c   He, W ^a   Mo, R ^a   Ramachandran, R ^a   Ramani, K ^c   Schonenberg, K ^a   Tsang, Y ^c   Wang, X ^a   Gribelyuk, M ^a   Yan, W ^a   Shepard, J ^a   Cartier, E ^d   Frank, M ^d   Harley, E ^a   Arndt, R ^a   Knarr, R ^a   Bailey, T ^a   Zhang, B ^a   Wong, K ^a   Graves Abe, T ^a   Luckowski, E ^b   Park, D G ^d   Narayanan, V ^d   Chudzik, M ^a   Khare, M ^a   more..

^a IBM RESEARCH   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

^c ADVANCED MICRO DEVICES   (United States)

^d IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AC DRIVES; ADDITIONAL STRESS; CMOS DEVICES; DRIVE CURRENTS; DUAL STRESS LINERS; GATE LENGTH SCALING; GATE LENGTHS; HIGH DRIVE CURRENTS; INTEGRATION SCHEMES; METAL GATE STACKS; METAL GATES; OFF CURRENTS; PROCESS FLOWS; SOI CMOS; SOI TECHNOLOGIES;

CMOS INTEGRATED CIRCUITS; ELECTRON DEVICES; SCALABILITY;

FIELD EFFECT TRANSISTORS;

EID: 64549106033     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796774     Document Type: Conference Paper

References (7)

1. F. Andrieu et al. IEDM, Tech. Digest, 2006.
2. E. Gusev, V. Narayanan, M. Frank, IBM J. Res. & Dev. Vol. 50 (4-5) pp. 387-410 Jul-Sep. 2006
3. K. Mistry et al, IEDM 2007, p. 247.
4. S. Mayazumi et al, IEDM 2007, p. 293
5. M Chudzik et al. VLSI Tech. Dig., p.194, 2007.
6. S. Narasimha et. al, IEDM Tech. Digest, 2006.
7. Y. Taur, and T. Ning, Fundamentals of Modern VLSI Devices, Pg 16, 1998.