Nanometer MOSFET effects on the minimum-energy point of sub-45nm subthreshold logic-mitigation at technology and circuit levels

ACM Transactions on Design Automation of Electronic Systems

Volumn 16, Issue 1, 2010, Pages

  Bol, David ^a   Flandre, Denis ^a   Legat, Jean Didier ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

CMOS digital integrated circuits; Leakage current; Short channel effects; Silicon On Insulator (SOI) technology; Subthreshold logic; Ultra low power; Variability

Indexed keywords

CMOS DIGITAL INTEGRATED CIRCUITS; SHORT-CHANNEL EFFECT; SILICON-ON-INSULATOR (SOI) TECHNOLOGY; SUBTHRESHOLD LOGIC; ULTRA-LOW POWER; VARIABILITY;

CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC BATTERIES; ENERGY UTILIZATION; INTEGRATED CIRCUITS; LEAKAGE CURRENTS; MOSFET DEVICES; SEMICONDUCTING SILICON COMPOUNDS; SILICON ON INSULATOR TECHNOLOGY; TECHNOLOGY; THRESHOLD ELEMENTS;

LOGIC CIRCUITS;

EID: 78650293307     PISSN: 10844309     EISSN: 15577309     Source Type: Journal    
DOI: 10.1145/1870109.1870111     Document Type: Article

References (41)

1. ASENOV, A., BROWN, A., DAVIES, J., KAYA, S., AND SLAVCHEVA, G. 2003. Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale mosfets. IEEE Trans. Electron. Devices 50, 9, 1837-1852.
2. BOL, D., AMBROISE, R., FLANDRE, D., AND LEGAT, J.-D. 2008. Sub-45nm fully-depleted soi cmos subthreshold logic for ultra-low-power applications. In Proceedings of the International SOI Conference. IEEE, 57-58.
3. BOL, D., AMBROISE, R., FLANDRE, D., AND LEGAT, J.-D. 2009a. Interests and limitations of technology scaling for subthreshold logic. IEEE Trans. VLSI Syst. 17, 10, 1508-1519.
4. BOL, D., FLANDRE, D., AND LEGAT, J.-D. 2009b. Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits. In Proceedings of the International Symposium on Low-Power Electronics and Design. ACM, 21-26.
5. BOL, D., KAMEL, D., FLANDRE, D., AND LEGAT, J.-D. 2009c. Nanometer mosfet effects on the minimum-energy point of 45nm subthreshold logic. In Proceedings of the International Symposium on Low-Power Electronics and Design. ACM, 3-8.
6. BOL, D.,HOCQUET, C., FLANDRE, D., AND LEGAT, J.-D. 2010. Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits. In Proceedings of the International Circuits and Systems Conference. IEEE, 1484-1487.
7. BROWN, A. R., ROY, G., AND ASENOV, A. 2007. Poly-si-gate-related variability in decananometer mosfets with conventional architecture. IEEE Trans. Electron. Devices 54, 11, 3056-3063.
8. CALHOUN, B. AND CHANDRAKASAN, A. 2006. Ultra-dynamic voltage scaling (udvs) using subthreshold operation and local voltage dithering. IEEE J. Solid-State Circ. 41, 1, 238-245.
9. CALHOUN, B., WANG, A., AND CHANDRAKASAN, A. 2005. Modeling and sizing for minimum energy operation in subthreshold circuits. IEEE J. Solid-State Circ. 40, 9, 1778-1786.
10. CAO, Y. AND CLARK, L. 2005. Mapping statistical process variations toward circuit performance variability: An analytical modeling approach. In Proceedings of the Design Automation Conference. ACM, 658-663.
11. CHANDRAKASAN, A., DALY, D., FINCHELSTEIN, D., KWONG, J., RAMADASS, Y., SINANGIL, M., SZE, V., AND VERMA, N. 2010. Technologies for ultradynamic voltage scaling. Proc. IEEE 98, 2, 191-241.
12. CHENG, B., ROY, S., BROWN, A., MILLAR, C., AND ASENOV, A. 2008. Statistical variations in 32nm thin-body sol devices and sram cells. In International Conference on Solid-State and Integrated-Circuit Technology. IEEE.
13. COLINGE, J. P. 2004. The soi mosfet. In Silicon-on-Insulator Technology: Materials to VLSI, 3rd. Springer, 151-246.
14. 2 6t-sram bitcell. In Proceedings of the International Electronics Device Meeting. IEEE, 267-270.
15. HANSON, S., ZHAI, B., BLAUW, D., AND SYLVESTER, D. 2006. Energy optimality and variability in subthreshold design. In Proceedings of the International Symposium on Low-Power Electronics and Design. ACM, 363-365. (Pubitemid 46609767)
16. HANSON, S., SEOK, M., SYLVESTER, D., AND BLAUW, D. 2008. Nanometer device scaling in subthreshold logic and sram. IEEE Trans. Electron. Devices 55, 1, 175-185.
17. KAUL, H., ANDERS, M., MATHEW, S., HSU, S., AGARWAL, A., KRISHNAMURTHY, R., AND BORKAR, S. 2010. A 300mv 494gops/w reconfigurable dual-supply 4-way simd vector processing accelerator in 45nm cmos. IEEE J. Solid-State Circ. 45, 1, 95-102.
18. KIM, J.-J. AND ROY, K. 2004. Double-gate mosfet subthreshold circuit for ultralow power applications. IEEE Trans. Electron. Devices 51, 9, 1468-1474.
19. KWONG, J., RAMADASS, Y., VERMA, N., AND CHANDRAKASAN, A. 2009. A 65nm sub-vt microcontroller with integrated sram and switched capacitor dc-dc converter. IEEE J. Solid-State Circ. 44, 1, 115-126.
20. MIZUNO, T., OKAMURA, J., AND TORIUMI, A. 1993. Experimental study of threshold voltage fluctuations using an 8k mosfets array. In Proceedings of the Symposium on VLSI Technology. IEEE, 41-42.
21. MOHAPATRA, N., DESAI, M., NARENDRA, S., AND RAMGOPAL, V. R. 2003. Modeling of parasitic capacitances in deep submicrometer conventional and high-dielectric mos transistors. IEEE Trans. Electron. Devices 50, 4, 959-966.
22. NUMATA, T. AND TAKAGI, S. 2004. Device design for subthreshold slope and threshold voltage control in sub-100-nm fully-depleted soi mosfets. IEEE Trans. Electron. Devices 51, 12, 2161-2167.
23. PAUL, B. AND ROY, K. 2008. Oxide thickness optimization for digital subthreshold operation. IEEE Trans. Electron. Devices 55, 2, 685-688.
24. PAUL, B., RAYCHOWDHURY, A., AND ROY, K. 2005. Device optimization for digital subthreshold logic operation. IEEE Trans. Electron. Devices 52, 2, 237-247.
25. PAUL, B. C., BANSAL, A., AND ROY, K. 2006. Underlap dgmos for digital subthreshold operation. IEEE Trans. Electron. Devices 53, 4, 910-913.
26. PELGROM, M., DUINMAIJER, A., AND WELBERS, A. 1989. Matching properties of mos transistors. IEEE J. Solid-State Circ. 24, 5, 1433-1440.
27. PU, Y., DE GYVEZ, J., CORPORAAL, H., AND HA, Y. 2009. An ultra-low-energy/frame multistandard jpeg co-processor in 65nm cmos with sub/near-threshold power supply. In Proceedings of the International Solid-State Circuit Conference. IEEE, 146-147.
28. RAYCHOWDHURY, A., FONG, X., CHEN, Q., AND ROY, K. 2006. Analysis of super cut-off transistors for ultra-low power digital circuits. In Proceedings of the International Symposium on Low-Power Electronics and Design. ACM, 2-7.
29. ROY, G., BROWN, A. R., ADAMU-LEMA, F., ROY, S., AND ASENOV, A. 2006. Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nanomosfets. IEEE Trans. Electron. Devices 53, 12, 3063-3070.
30. SEOK, M., HANSON, S., SYLVESTER, D., AND BLAUW, D. 2007. Analysis and optimization of sleep modes in subthreshold circuit design. In Proceedings of the Design Automation Conference. ACM, 604-699.
31. SKOTNICKI, T., FENOUILLET-BERANGER, C., GALLON, C., BOEUF, F., MONFRAY, S., PAYET, F., POUYDEBASQUE, A., SZCZAP, M., FARCY, A., ARNAUD, F., CLERC, S., SELLIER, M., CATHIGNOL, A., SCHOELLKOPF, J.-P., PEREA, E., FERRANT, R., AND MINGAM, H. 2008. Innovative materials, devices and cmos technologies for low-power mobile multimedia. IEEE Trans. Electron. Devices 55, 1, 96-130.
32. SOELEMAN, H. AND ROY, K. 1999. Ultra-Low power digital subthreshold logic circuits. In Proceedings of the International Symposium on Low-Power Electronics and Design. ACM, 94-96.
33. SZE, V. AND CHANDRAKASAN, A. 2006. A 0.4-v uwb baseband processor. In Proceedings of the International Symposium on Low-Power Electronics and Design. ACM, 262-267.
34. TAKAHASHI, O., ADAMS, C., BEHNEN, E., CHIANG, O., COTTIER, S., COULMAN, P., CULP, J., GERVAIS, G., GRAY, M., ITAKA, Y., JOHNSON, C., KONO, F., L.MAURICE, MCCULLEN, K., NGUYEN, L., NISHINO, Y., NORO, H., PILLE, J., RILEY, M., TOKITO, S., T.WAGNER, AND YOSHIHARA, H. 2008. Migration of cell broadband engine from 65nm soi to 45nm soi. In Proceedings of the International Solid-State Circuit Conference. IEEE, 86-87.
35. TSUTSUI, G., SAITOH, M., NAGUMO, T., AND HIRAMOTO, T. 2005. Impact of soi thickness fluctuation on threshold voltage variation in ultra-thin body soi mosfets. IEEE Trans. Nanotechnol. 40, 3, 369-373.
36. VERMA, N., KWONG, J., AND CHANDRAKASAN, A. 2008. Nanometer mosfet variation in minimum energy subthreshold circuits. IEEE Trans. Electron. Devices 55, 1, 163-174.
37. VITALE, S., WYATT, P., CHECKA, N., KEDZIERSKI, J., AND KEAST, C. 2010. Fdsoi process technology for subthreshold-operation ultralow-power electronics. Proc. IEEE 98, 2, 333-342.
38. WEBER, O. 2008. High immunity to threshold voltage variability in undoped ultra-thin fdsoi mosfets and its physical understanding. In Proceedings of the International Electron Device Meeting. IEEE.
39. ZHAI, B., BLAUW, D., SYLVESTER, D., AND FLAUTNER, K. 2005. The limit of dynamic voltage scaling and insomniac dynamic voltage scaling. IEEE Trans. VLSI Syst. 13, 11, 1239-1252.
40. ZHAI, B., DRESLINSKI, R., BLAAUW, D., MUDGE, T., AND SYLVESTER, D. 2007. Energy efficient near-threshold chip multi-processing. In Proceedings of the International Symposium on Low- Power Electronics and Design. ACM, 32-37.
41. ZHAO, W. AND CAO, Y. 2006. New generation of predictive technology model for sub-45nm early design exploration. IEEE Trans. Electron. Devices 53, 11, 2816-2823.