FDSOI process technology for subthreshold-operation ultralow-power electronics

Proceedings of the IEEE

Volumn 98, Issue 2, 2010, Pages 333-342

  Vitale, Steven A ^a   Wyatt, Peter W ^a   Hecka, Nisha ^a   Kedzierski, Jakub ^a   Keast, Craig L ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Low power; Metal gate; Silicon on insulator (SOI); Subthreshold

Indexed keywords

ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY GAP; POWER ELECTRONICS; THRESHOLD ELEMENTS;

LOW POWER; LOW POWER DESIGN TECHNIQUE; METAL GATE; SILICON ON INSULATOR DEVICES; SILICON-ON- INSULATORS (SOI); SUBTHRESHOLD; TECHNOLOGICAL CAPABILITY; ULTRA-LOW-POWER ELECTRONICS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 75649146252     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2009.2034476     Document Type: Article

References (31)

1. D. Bol, R. Ambroise, D. Flandre, and J.-D. Legar, "Sub-45 nm fully-depleted SOI CMOS subthreshold logic for ultra-low-power applications, "in 2008 IEEE Int. SOI Conf. Proc., Oct. 2008, pp. 57-58.
2. A. Uchiyama, S. Baba, Y. Nagatomo, and J. Ida, "Fully depleted SOI technology for ultra low power digital and RF applications, "in 2006 IEEE Int. SOI Conf. Proc., Oct. 2006, pp. 15-16.
3. B. H. Calhoun, D. C. Daly, N. Verma, D. F. Finchelstein, D. D. Wentzloff, A. Wang, S.-H. Cho, and A. P. Chandrakasan, "Design considerations for ultra-low energy wireless microsensor nodes, "IEEE Trans. Comput., vol.54, pp. 727-740, Jun. 2005.
4. A. Ebina, T. Kadowaki, Y. Sato, and M. Yamaguchi, "Ultra low-power CMOS IC using partially-depleted SOI technology, "in Proc. Custom Integrated Circuits Conf., May 2000, pp. 57-60.
5. J. Cai, Z. Ren, A. Majumdar, T. H. Ning, H. Yin, D.-G. Park, and W. E. Haensch, "Will SOI have a life for the low-power market?[in 2008 IEEE Int. SOI Conf. Proc., Oct. 2008, pp. 15-16.
6. M. Gouker, MIT Lincoln Laboratory. Private Communication.
7. J.-L. Pelloie, "SOI for low-power low-voltageVBulk versus SOI, "Microelectronic Engineering, vol.39, pp. 155-166, 1997.
8. E. Vittoz, "Micropower techniques, "in Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing, J. Franca and Y. Tsividis, Eds. Englewood Cliffs, NJ: Prentice-Hall, 1994.
9. J. L. Pelloie, C. Raynaud, O. Faynot, A. Grouillet, and J. Du Port de Pntcharra, "CMOS/SOI technologies for low-power and low-voltage circuits, "Microelectronic Engineering, vol.48, pp. 327-334, 1999.
10. H. Shimada, Y. Hirano, T. Ushiki, K. Ino, and T. Ohmi, "Tantalum-gate thin-film SOI nMOS and pMOS for low-power applications, "IEEE Trans. Electron Devices, vol.44, pp. 1903-1907, 1997.
11. K. Roy, H. Mahmoodi, S. Mukhopadhyay, H. Ananthan, A. Bansai, and T. Cakici, BDouble-gate SOI devices for low-power and high-performance applications, "in Proc. 19th Int. Conf. VLSI Design, Jan. 2006, pp. 445-452.
12. E. Simoen and C. Claeys, "The cryogenic operation of partially depeleted silicon-on-insulator inverters, "IEEE Trans. Electron Devices, vol.42, pp. 1100-1105, Jun. 1995.
13. Y. Li, G. Niu, J. D. Cressler, J. Patel, S. T. Liu, R. A. Reed, M. M. Mojarradi, and B. J. Blalock, "The operation of 0.35 jim partially depleted SOI CMOS technology in extreme environments, "Solid-State Electron., vol.47, pp. 1111-1115, 2003.
14. V. P. Trivedi and J. G. Fossum, "Scaling fully depleted SOI CMOS, "IEEE Trans. Electron Devices, vol.50, pp. 2095-2103, 2003.
15. T. C. Hsiao, A. W. Wang, K. Saraswat, and J. C. S. Woo, "An alternative gate electrode material of fully depleted SOI CMOS for low power applications, "in Proc. 1997 IEEE Int. SOI Conf., Oct. 1997, pp. 20-21.
16. H. Shang and M. H. White, "An ultra-thin midgap gate FDSOI MOSFET, "Solid State Electron., vol.44, pp. 1621-1625, 2000.
17. J. Chen, ". Maiti, D. Connelly, M. Mendicino, F. Huang, O. Adetutu, Y. Yu, D. Weddington, W. Wu, J. Canelaria, D. Dow, P. Tobin, and J. Mogab, "0.18 jim metal gate fully-depleted SOI MOSFETs for advanced CMOS application," in 1999 Symp. VLSI Technol. Dig. Tech. Papers, 1999, pp. 25-26.
18. H. Shimada, T. Ushiki, Y. Hirano, and T. Ohmi, "Tantalum-gate SOI MOSFET's featuring excellent threshold voltage control in low-power applications," in Proc. 1995 IEEE Int. SOI Conf., Oct. 1995, pp. 96-97.
19. Y. Liu, S. Kijima, E. Sugimata, M. Masahara, K. Endo, T. Matsukawa, K. Ishii, K. Sakamoto, T. Sekigawa, H. Yamauchi, Y. Takanashi, and E. Suzuki, "Investigation of the TiN gate electrode with tunable work function and its application for FinFET fabrication," IEEE Trans. Nanotechnol., vol.5, pp. 723-726, Nov. 2006.
20. R. Singanamalla, J. Lisoni, I. Ferain, O. Richard, L. Carbonell, T. Schram, H. Y. Yu, S. Kubicek, S. De Gendt, M. Jurczak, and K. De Meyer, "Electrical and material evaluation of the MOCVD TiN as metal gate electrode for advanced CMOS technology," in Mater. Res. Soc. Symp. Proc, 2006, vol.917, pp. 174-197.
21. C. Fenouillet-Beranger, S. Denorme, ". Icard, F. Boeuf, J. Coignus, O. Faynot, L. Brevard, C. Buj, C. Soonekindt, J. Todeschini, J.C. Le-Denmat, N. Loubet, C. Gallon, P. Perreau, S. Manakli, M Mghetti, L. Pain, V. Arnal, A. Vandooren, D. Aime, L. Tosti, C. Savardi, F. Martin, T. Salvetat, S. Lhostis, C. Laviron, N. Auriac, T. Kormann, G. Chabanne, S. Gaillard, O. Belmont, E. Laffosse, D. Barge, A. Zauner, A. Tarnowka, K. Romanjec, H. Brut, A. Lagha, S. Bonnetier, F. Joly, N. Mayet, A. Cathignol, D. Galpin, D. Pop, R. Delsol, R. Pantel, F. Pionnier, G. Thomas, D. Bensahel, S. Deleombus, T. Skotnicki, and H. Mmgam, "Fully-depleted SOI technology using high-K and single-metal gate for 32 nm node LSTP applications featuring 0.179 jim 6T-SRAM bitcell," in Tech. Dig. Int. Electron Devices Meeting (IEDM), Dec. 2007, pp. 267-270.
22. F. Andrieu, C. Dupre, F. Rochette, O. Faynot, L. Tosti, C. Buj, E. Rouchouze, M. Casse, B. Ghyselen, I. Cayrefoureq, L. Brevard, F. Allain, J. C. Barbe, J. Cluzel, A. Vandooren, S. Denorme, T. Ernst, C. Fe nouillet-Beranger, C. Jahan, D. Lafond, H. Dansas, ". Previtali, J. P. Colonna, H. Grampeix, P. Gaud, C. Mazure, and S. Deleonibus, "25 nm short and narrow strained FDSOI with TiN/HfO2 gate stack," in 2006 Symp. VLSI Technol. Dig. Tech. Papers, 2006, pp. 134-135.
23. V. Barral, T. Poiroux, F. Andrieu, C. Buj-Dufournet, O. Faynot, T. Ernst, L. Brevard, C. Fenouillet-Beranger, D. Lafond, J.M. Hartmann, V. Vidal, F. Allain, N. Daval, I. Cayrefourcq, L. Tosti, D. Munteanu, J.L. Autran, and S. Deleonibus, "Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack," in Tech. Dig. Int. Electron Devices Meeting (IEDM), Dec. 2007, pp. 61-64.
24. B. Doris, Y. H. Kim, ". P. Linder, M. Steen, V. Narayanan, D. Boyd, J. Rubino, L. Chang, J. Sleight, A. Topol, E. Sikorski, L. Shi, L. Wong, K. Babich, Y. Zhang, P. Kirsch, J. Newbury, J. F. Walker, R. Carruthers, C. D'Emic, P. Kozlowski, R. Jammy, K. W. Guarini, and M. Leong, "High performance FDSOI CMOS technology with metal gate and high-k," in 2005 Symp. VLSI Technol. Dig. Techn. Papers, 2005, pp. 214-215. (Pubitemid 43897628)
25. 2 as a metal gate stack for FDSOI cMOSFETs down to 25 nm gate length and width, "in IEDM Tech. Dig., 2006, 23.7.
26. 2 gate stack, "in 2005 Symp. VLSI Technol. Dig. Tech. Papers, 2005, pp. 108-109.
27. N. Yang, W. K. Henson, J. R. Hauser, and J. J. Wortman, "Modeling study of ultrathin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices, "IEEE Trans. Electron Devices, vol.46, pp. 1464-1471, Jul. 1999.
28. S. A. Vitale, J. Kedzierski, P. Healey, N. Checka, P. W. Wyatt, and C. L. Keast, "Workfunction-tuned TiN metal gate FDSOI transistors for subthreshold operation, "IEEE Trans. Electron Devices, in review.
29. A. B. Sachid, C. R. Manoj, D. K. Sharma, and V. R. Rao, "Gate fringe-induce barrier lowering in underlap FinFET structures and its optimization, "IEEE Electron Device Letters, vol.20, pp. 128-130, Jan. 2008.
30. A. Kranti, Y. Hao, and G. A. Armstrong, "Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications, "Semicond. Sci. Technol., vol.23, pp. 1-13, 2008.
31. D. Connelly, P. Clifton, C. Faulker, and D. E. Grupp, "Ultra-thin-body fully depleted SOI metal source/drain n-MOSFETs and ITRS low-standby-power targets through 2018, "in IEEE Int. Electron Devices Meeting (IEDM) Tech. Dig., Dec. 2005, pp. 972-975.