Poly-Si-gate-related variability in decananometer MOSFETs with conventional architecture

IEEE Transactions on Electron Devices

Volumn 54, Issue 11, 2007, Pages 3056-3063

  Brown, Andrew R ^a   Roy, Gareth ^a   Asenov, Asen ^a  

^a UNIVERSITY OF GLASGOW   (United Kingdom)

Author keywords

Fermi level pinning; MOSFETs; Polysilicon (poly Si) grain boundaries; Variability

Indexed keywords

COMPUTER SIMULATION; FERMI LEVEL; GATES (TRANSISTOR); GRAIN BOUNDARIES; GRAIN SIZE AND SHAPE; MOSFET DEVICES; STATISTICAL METHODS; THRESHOLD VOLTAGE;

DECANANOMETER; LINE-EDGE ROUGHNESS; RANDOM DISCRETE DOPANTS;

POLYSILICON;

EID: 36248947996     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.907802     Document Type: Article

References (33)

1. G. Decklerk, "A look into the future of nanoelectronics," in VLSI Symp. Tech. Dig., 2005, pp. 6-10.
2. K. Bernstein, D. J. Frank, A. E. Gattiker, W. Haensch, B. L. Ji, S. R. Nassif, E. J. Nowak, D. J. Pearson, and N. J. Rohrer, "High-performance CMOS variability in the 65-nm regime and beyond," IBM J. Res. Develop., vol. 50, no. 4/5, pp. 433-449, Jul. 2006.
3. A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva, "Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 9, pp. 1837-1852, Sep. 2003.
4. B.-J. Cheng, S. Roy, and A. Asenov, "The impact of random doping effects on CMOS SRAM cell, in Proc. 30th ESSCIRC, Leuven, Belgium, 2004, pp. 219-222.
5. A. Agarwal, K. Chopra, V. Zolotov, and D. Blaauw, "Circuit optimization using statistical static timing analysis," in Proc. 42nd Des. Autom. Conf., Anaheim, CA, 2005, pp. 321-324.
6. T. Scotnicki, "Nano-CMOS and emerging technologies - Myths and hopes," in Proc. Int. Conf. SSDM, Yokohama, Japan, 2006, pp. 2-5.
7. D. J. Frank, Y. Taut, M. Ieong, and H.-S. P. Wong, "Monte-Carlo modeling of threshold variation due to dopant fluctuations," in Proc. Symp. VLSI Technol. Dig. Tech. Papers, 1999, pp. 171-172.
8. P. A. Stolk and D. B. M. Klaasen, "The effect of statistical dopant fluctuations on MOS device performance," in IEDM Tech. Dig. Papers 1996, pp. 627-630.
9. A. Asenov, "Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFETs: A 3-D 'atomistic' simulation study," IEEE Trans. Electron Devices, vol. 45, no. 12, pp. 2505-2513, Dec. 1998.
10. T. Linton, M. Giles, and P. Packan, "The impact of line edge roughness on 100 nm device performance," in Proc. Silicon Nanoelectronics Workshop, 1998, pp. 82-83.
11. P. Oldiges, Q. Lin, K. Pertillo, M. Sanchez, M. Ieong, and M. Hargrove, "Modelling line edge roughness effects in sub 100 nm gate length devices," in Proc. SISPAD, Seattle, WA, 2000, pp. 131-134.
12. A. Asenov, S. Kaya, and A. R. Brown, "Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness," IEEE Trans. Electron Devices, vol. 50, no. 5, pp. 1254-1260, May 2003.
13. A. Asenov, S. Kaya, and J. H. Davies, "Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations," IEEE Trans. Electron Devices, vol. 49, no. 1, pp. 112-119, Jan. 2002.
14. A. R. Brown, J. R. Watling, A. Asenov, G. Bersuker, and P. Zeitzoff, "Intrinsic parameter fluctuations in MOSFETs due to structural non-uniformity of high-κ gate stack materials," in Proc. Int. Conf. SISPAD, Tokyo, Japan, 2005, pp. 27-30. IEEE Cat. 05TH8826.
15. A. R. Brown, J. R. Watling, and A. Asenov, "Intrinsic parameter fluctuations due to random grain orientations in high-κ, gate stacks," J. Comput. Electron., vol. 5, no. 4, pp. 333-336, Dec. 2006.
16. A. Asenov and S. Saint, "Polysilicon gate enhancement of the random dopant induced threshold voltage fluctuations in sub 100 nm MOSFETs with ultrathin gate oxide," IEEE Trans. Electron Devices, vol. 47, no. 4, pp. 805-812, Apr. 2000.
17. R. Difrenza, J. C. Vildeuil, P. Llinares, and G. Ghibaudo, "Impact of grain number fluctuations in MOS transistor gate on matching performance," in Proc. Int. Conf. Microelectron. Test Struct., Monterey, CA, 2003, pp. 244-249.
18. Y. Okayama, T. Saito, K. Nakajima, S. Taniguchi, T. Ono, K. Nakayama, R. Watanabe, A. Oishi, A. Eiho, T. Komoda, T. Kimura, M. Hamaguchi, Y. Takegawa, T. Aoyama, T. Iinuma, K. Fukasaku, R. Morimoto, K. Oshima, K. Oono, M. Saito, M. Iwai, S. Yamada, N. Nagashima, and F. Matsuoka, "Suppression effects of threshold voltage variation with Ni FUSI gate electrode for 45 nm node and beyond LSTP and SRAM devices," in VLSI Symp. Tech. Dig., 2006, pp. 96-97.
19. H. Watanabe, "Statistics of grain boundaries in polysilicon," IEEE Trans. Electron Devices, vol. 54, no. 1, pp. 38-44, Jan. 2007.
20. H. P. Tuinhout, "Impact of parametric mismatch and fluctuations on performance and yield of deep-submicron CMOS technologies," in Proc. 32nd ESSDERC, Firenze, Italy, 2002, pp. 95-101.
21. M. Hane, T. Ikezawa, and T. Ezaki, "Atontistic 3D process/device simulation considering gate line edge roughness and poly-Si random crystal orientation effects," in IEDM Tech. Dig. Papers, 2003, pp. 9.5.1-9.5.4.
22. H. Fukutome, Y. Momiyama, T. Kubo, E. Yoshida, H. Morioka, M. Tajima, and T. Aoyama, "Suppression of poly-gate-induced fluctuations in carrier profiles of sub-50 nm MOSFETs," in IEDM Tech. Dig. Papers 2006, pp. 1-4.
23. A. Cathignol, K. Rochereau, and G. Glubaudo, "Impact of a single grain boundary in the polycrystalline silicon gate on sub 100 nm bulk MOSFET characteristics - Implication on matching properties," in Proc. 7th Eur. Workshop ULIS, Grenoble, France, 2006, pp. 145-148.
24. G. Roy, A. R. Brown, F. Adamu-Lema, S. Roy, and A. Asenov, "Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETs," IEEE Trans. Electron Devices, vol. 53, no. 12, pp. 3063-3070, Dec. 2006.
25. A. Asenov, A. R. Brown, J. H. Davies, and S. Saint, "Hierarchical approach to 'atomistic' 3-D MOSFET simulation," IEEE Trans. Comput.- Aided Design Integr. Circuits Syst., vol. 18, no. 11, pp. 1558-1565, Nov. 1999.
26. S. Uma, A. D. McConnell, M. Asheghi, K. Kurabayashi, and K. E. Goodson, "Temperature-dependent thermal conductivity of undoped polycrystalline silicon layers," Int. J. Thermophys., vol. 22, no. 2, pp. 605-616, Mar. 2001.
27. A. Cathignol and G. Ghibaudo, personal communication.
28. P. M. Walker, H. Mizuta, S. Uno, Y. Furuta, and D. G. Hasko, "Improved OFF-current and subthreshold slope in aggressively scaled poly-Si TFTs with a single grain boundary in the channel," IEEE Trans. Electron Devices, vol. 511, no. 2, pp. 212-219, Feb. 2004.
29. A. R. Brown, G. Roy, and A. Asenov, "Impact of Fermi level pinning at polysilicon gate grain boundaries on nano-MOSFET variability: A 3-D simulation study," in Proc. 36th ESSDERC, Montreux, Switzerland, 2006, pp. 451-454.
30. S. Inaba, K. Okano, S. Matsuda, M. Fujiwara, A. Hokazono, K. Adachi, K. Ohuchi, H. Suto, H. Fukui, T. Shimizu, S. Mori, H. Oguma, A. Murakoshi, T. Itani, T. Iinuma, T. Kudo, H. Shibata, S. Taniguchi, M. Takayanagi, A. Azuma, H. Oyamatsu, K. Suguro, Y. Katsumata, Y. Toyoshima, and H. Ishiuchi, "High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide," IEEE Trans. Electron Devices, vol. 49, no. 12, pp. 2263-2270, Dec. 2002.
31. Fukutome, Y. Momiyama, Y. Tagawa, T. Kubo, T. Aoyama, H. Arimoto, and Y. Nara, "Direct measurement of effects of shallow-trench isolation on carrier profiles in sub-50 nm n-MOSFETs," in Proc. Symp. VLSI Technol. Dig. Tech. Papers, 2005, pp. 140-141.
32. F. Arnaud, B. Duriez, B. Tavel, L. Pain, J. Todeschini, M. Jurdit, Y. Laplanche, F. Boeuf, F. Salvetti, D. Lenoble, J. P. Reynard, F. Wacquant, P. Morin, N. Emonet, D. Barge, M. Bidaud, D. Ceccarelli, P. Vannier, Y. Loquet, H. Leninger, F. Judong, C. Perrot, I. Guilmeau, R. Palla, A. Beverina, V. DeJonghe, M. Broekaart, V. Vachellerie, R. A. Bianchi, B. Borot, T. Devoivre, N. Bicais, D. Roy, M. Denais, K. Rochereau, R. Difrenza, N. Planes, H. Brut, L. Vishnobulta, D. Reber, P. Stolk, and M. Woo, "Low cost 65 nm CMOS platform for low power & general purpose applications," in Proc. Symp. VLSI Technol. Dig. Tech. Papers, 2004, pp. 10-11.
33. A. V.-Y Thean, Z.-H. Slu, L. Mathew, T. Stephens, H. Desjardin, C. Parker, T. White, M. Stoker, L. Prabhu, R. Garcia, B.-Y. Nguyen, S. Murphy, R. Rai, J. Conner, B. E. White, and S. Venkatesan, Performance and variability comparisons between multi-gate FETs and planar SOI transistors," in IEDM Tech. Dig. Papers, 2006, pp. 1-4.