Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2009, Pages 3-8

  Bol, David ^a   Kamel, Dina ^a   Flandre, Denis ^a   Legat, Jean Didier ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

CMOS digital integrated circuits; Gate leakage; Short channel effects; Subthreshold logic; Ultra low power; Variability

Indexed keywords

CMOS DIGITAL INTEGRATED CIRCUITS; GATE LEAKAGES; SHORT-CHANNEL EFFECT; SUBTHRESHOLD LOGIC; ULTRA-LOW POWER;

CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRON BEAM LITHOGRAPHY; INTEGRATED CIRCUITS; LOW POWER ELECTRONICS; MOS CAPACITORS; MOSFET DEVICES; POWER ELECTRONICS;

LOGIC CIRCUITS;

EID: 70449704647     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1594233.1594237     Document Type: Conference Paper

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