Interests and limitations of technology scaling for subthreshold logic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 10, 2009, Pages 1508-1519

  Bol, David ^a   Ambroise, Renaud ^a   Flandre, Denis ^a   Legat, Jean Didier ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

CMOS digital integrated circuits; Subthreshold logic; Technology scaling; Ultralow power (ULP); Variability

Indexed keywords

CMOS DIGITAL INTEGRATED CIRCUITS; SUBTHRESHOLD LOGIC; TECHNOLOGY SCALING; ULTRALOW POWER (ULP); VARIABILITY;

CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ENERGY EFFICIENCY; ENERGY GAP; INTEGRATED CIRCUITS; NANOTECHNOLOGY; TECHNOLOGY; THROUGHPUT;

LOGIC CIRCUITS;

EID: 70349736169     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2005413     Document Type: Article

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