메뉴 건너뛰기




Volumn , Issue , 2007, Pages 32-37

Energy efficient near-threshold chip multi-processing

Author keywords

CMP; Energy efficient; Near threshold; Subthreshold

Indexed keywords

CMP; NEAR THRESHOLD; SUBTHRESHOLD;

EID: 36949010083     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1283780.1283789     Document Type: Conference Paper
Times cited : (78)

References (17)
  • 1
    • 34547375943 scopus 로고    scopus 로고
    • A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency
    • B. Zhai, L. Nazhandali, et al., "A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency", IEEE VLSI Technology and Circuits, 2006
    • (2006) IEEE VLSI Technology and Circuits
    • Zhai, B.1    Nazhandali, L.2
  • 2
    • 28144443325 scopus 로고    scopus 로고
    • A 180mV FFT processor using subthreshold circuits techniques
    • A. Wang, A. Chandrakasan, "A 180mV FFT processor using subthreshold circuits techniques", IEEE ISSCC 2004
    • (2004) IEEE ISSCC
    • Wang, A.1    Chandrakasan, A.2
  • 3
    • 36949021263 scopus 로고    scopus 로고
    • B. Zhai, D. Blaauw, et al., Theoretical and practical limits of dynamic voltage scaling, DAC2004
    • B. Zhai, D. Blaauw, et al., "Theoretical and practical limits of dynamic voltage scaling", DAC2004
  • 4
    • 84932103562 scopus 로고    scopus 로고
    • Characterizing and modeling minimum energy operation for subthreshold circuits
    • B. Calhoun, A. Chandrakasan, "Characterizing and modeling minimum energy operation for subthreshold circuits," ISLPED 2004
    • ISLPED 2004
    • Calhoun, B.1    Chandrakasan, A.2
  • 5
    • 0029179077 scopus 로고
    • The SPLASH-2 Programs: Characterization and Methodological Considerations
    • S. C. Woo, M. Ohara, et. al. "The SPLASH-2 Programs: Characterization and Methodological Considerations", ACMISCA, 1995.
    • (1995) ACMISCA
    • Woo, S.C.1    Ohara, M.2    et., al.3
  • 6
    • 36949028011 scopus 로고    scopus 로고
    • The Limit of Dynamic Voltage Scaling and Insomniac Dynamic Voltage Scaling
    • Nov
    • B. Zhai, D. Blaauw, et al., "The Limit of Dynamic Voltage Scaling and Insomniac Dynamic Voltage Scaling", IEEE TVLSI, Nov 2004
    • (2004) IEEE TVLSI
    • Zhai, B.1    Blaauw, D.2
  • 7
    • 0025415048 scopus 로고
    • Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
    • Apr
    • T. Sakurai and A. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEEJSSC, vol. 25, no. 2, pp. 584-594, Apr. 1990.
    • (1990) IEEEJSSC , vol.25 , Issue.2 , pp. 584-594
    • Sakurai, T.1    Newton, A.2
  • 8
    • 84858486203 scopus 로고    scopus 로고
    • http://www.arm.com/products/CPUs
  • 9
    • 84863734274 scopus 로고    scopus 로고
    • Scaling and Characterizing Database Workloads: Bridging the Gap between Research and Practice
    • R. A. Hankins, T. A. Diep, et al., "Scaling and Characterizing Database Workloads: Bridging the Gap between Research and Practice", IEEE/ACMMICRO 2003.
    • (2003) IEEE/ACMMICRO
    • Hankins, R.A.1    Diep, T.A.2
  • 10
    • 36949008473 scopus 로고    scopus 로고
    • Analysis and Mitigation of Variability in Subthreshold Design
    • B. Zhai, S. Hanson, et al., "Analysis and Mitigation of Variability in Subthreshold Design", IEEE ISLPED, 2005
    • (2005) IEEE ISLPED
    • Zhai, B.1    Hanson, S.2
  • 11
    • 36949021479 scopus 로고    scopus 로고
    • A 256kb Sub-threshold SRAM in 65nm CMOS
    • B. Calhoun and A. Chandrakasan, "A 256kb Sub-threshold SRAM in 65nm CMOS", IEEE ISSCC, 2006
    • (2006) IEEE ISSCC
    • Calhoun, B.1    Chandrakasan, A.2
  • 12
    • 36949008472 scopus 로고    scopus 로고
    • A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy
    • N. Verma, A. Chandrakasan, "A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy", IEEE ISSCC, 2007
    • (2007) IEEE ISSCC
    • Verma, N.1    Chandrakasan, A.2
  • 13
    • 37749048506 scopus 로고    scopus 로고
    • A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual-Ground Replica Scheme
    • T-H. Kim, J. Liu, et al., "A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual-Ground Replica Scheme", IEEE ISSCC, 2007
    • (2007) IEEE ISSCC
    • Kim, T.-H.1    Liu, J.2
  • 14
    • 36949000181 scopus 로고    scopus 로고
    • A Sub-200mV 6T SRAM in 0.13um CMOS
    • B. Zhai, D. Blaauw, et al., "A Sub-200mV 6T SRAM in 0.13um CMOS", IEEE ISSCC, 2007
    • (2007) IEEE ISSCC
    • Zhai, B.1    Blaauw, D.2
  • 15
    • 0024754187 scopus 로고
    • Matching properties of MOS transistors
    • M. J. M. Pelgrom, et al., "Matching properties of MOS transistors," IEEE JSSC, vol. 24, no. 5, pp. 1433-1440, 1989.
    • (1989) IEEE JSSC , vol.24 , Issue.5 , pp. 1433-1440
    • Pelgrom, M.J.M.1
  • 16
    • 33846535493 scopus 로고    scopus 로고
    • The M5 Simulator: Modeling Networked Systems
    • N. L. Binkert, R. G. Dreslinski, et al., "The M5 Simulator: Modeling Networked Systems.", IEEE Micro, pp. 52-60, 2006
    • (2006) IEEE Micro , pp. 52-60
    • Binkert, N.L.1    Dreslinski, R.G.2
  • 17
    • 84932088413 scopus 로고    scopus 로고
    • Single-Vdd and Single-Vt Super-Drowsy Techniques for Low-Leakage High-Performance Instruction Caches
    • N. S. Kim, K. Flautner, et al. "Single-Vdd and Single-Vt Super-Drowsy Techniques for Low-Leakage High-Performance Instruction Caches", IEEE/ACMISLPED, 2004.
    • (2004) IEEE/ACMISLPED
    • Kim, N.S.1    Flautner, K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.