Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Volumn , Issue , 2010, Pages 1484-1487

  Bol, David ^a   Hocquet, Cédric ^a   Flandre, Denis ^a   Legat, Jean Didier ^a  

^a UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

LEAKAGE REDUCTION; MODE ENERGIES; MOS-FET; NANOMETER TECHNOLOGY; NOISE MARGINS; POWER-GATING; SLEEP MODE; SLEEP TRANSISTORS; SUBTHRESHOLD CIRCUITS; SUBTHRESHOLD OPERATION; ULTRA-LOW POWER;

FABRICS; LEAKAGE CURRENTS; SLEEP RESEARCH; THRESHOLD ELEMENTS;

TRANSISTORS;

EID: 77956008372     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2010.5537352     Document Type: Conference Paper

References (11)

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