Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

IEEE Transactions on Electron Devices

Volumn 50, Issue 4, 2003, Pages 959-966

  Mohapatra, Nihar R ^b   Desai, Madhav P ^a   Narendra, Siva G ^a   Rao, V Ramgopal ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^b INTEL CORPORATION   (United States)

Author keywords

Fringing field; Gate insulator; High K dielectric; Monte Carlo methods; MOSFETs; Parasitic capacitance

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC GROUNDING; ELECTRODES; GATES (TRANSISTOR); MONTE CARLO METHODS; PERMITTIVITY; SILICA;

PARASITIC CAPACITANCE;

MOSFET DEVICES;

EID: 0038156181     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.811387     Document Type: Article

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