Clock rate versus IPC: The end of the road for conventional microarchitectures

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 2000, Pages 248-259

  Agarwal, Vikas ^a   Hrishikesh, M S ^a   Keckler, Stephen W ^a   Burger, Doug ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SYSTEMS PROGRAMMING; PIPELINE PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); TIMING CIRCUITS;

CAPACITY SCALING; MICROARCHITECTURE; PIPELINE SCALING;

COMPUTER ARCHITECTURE;

EID: 0033717865     PISSN: 08847495     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (31)