A low-radix and low-diameter 3D interconnection network design

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2009, Pages 30-41

  Xu, Yi ^a   Du, Yu ^b   Zhao, Bo ^a   Zhou, Xiuyi ^a   Zhang, Youtao ^b   Yang, Jun ^a  

^a PA 15260   (United States)

^b University of Pittsburgh   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARTS COMPUTING; COMPUTER ARCHITECTURE; INTEGRATED CIRCUIT INTERCONNECTS; INTERCONNECTION NETWORKS (CIRCUIT SWITCHING); MESH GENERATION; NETWORK LAYERS; NETWORK-ON-CHIP; ROUTERS; THREE DIMENSIONAL INTEGRATED CIRCUITS; TOPOLOGY;

3D STACKING TECHNOLOGY; DEEP SUB-MICRON TECHNOLOGY; ENERGY REDUCTION; INTERCONNECT DESIGN; NETWORK LATENCIES; ON CHIP COMMUNICATION; THROUGHPUT IMPROVEMENT; VERTICAL COMMUNICATIONS;

INTEGRATED CIRCUIT DESIGN;

EID: 65349146389     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2009.4798234     Document Type: Conference Paper

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