Implementation analysis of NoC: A MPSoC trace-driven approach

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn 2006, Issue , 2006, Pages 204-209

  Tota, Sergio ^a   Casu, Mario R ^a   Macchiarulo, Luca ^b  

^a POLITECNICO DI TORINO   (Italy)

^b UNIVERSITY OF HAWAII   (United States)

Author keywords

Deflection routing; Multiprocessor systems on chip; Networks on chip; Wormhole routing

Indexed keywords

ELECTRIC NETWORK TOPOLOGY; INTERCONNECTION NETWORKS;

DEFLECTION ROUTING; MULTIPROCESSOR SYSTEMS-ON-CHIP; NETWORKS ON CHIP; WORMHOLE ROUTING;

CHIP SCALE PACKAGES;

EID: 33750908258     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. L. Benini and G. De Micheli, "Networks on Chips: A New SoC Paradigm," IEEE Computer, Jan. 2002, pp. 70-78.
2. P.P. Pande et al., "Design, synthesis, and test of networks on chips," IEEE Design & Test of Computers, Sept .-Oct. 2005 pp. 404-413.
3. W. J. Dally, "Virtual-Channel Flow Control," IEEE Trans. Par. Dist. Sys., vol. 3, No. 2, Mar. 1992, pp. 194-205.
4. N.Genko et al., "A novel approach for network on chip emulation," ISCAS 2005, May 2005, pp. 2365-2368, Vol. 3.
5. P.P. Pande et al. "Performance evaluation and design trade-offs for network-on-chip interconnect architectures," IEEE Transactions on Computers, Vol. 54, Issue 8, Aug. 2005, pp. 1025-1040.
6. F. Borgonovo, "Deflection Routing," in [7] pp. 263-305.
7. M. Steenstrup, ed., Routing in Communication Networks, Prentice Hall, 1995.
8. http://www.tensilica.com/products/xtensa-LX.htm
9. "Deadlock-free Message Routing in Multiprocessor Interconnection Networks," IEEE Trans. Computers, Vol. C-36, No. 5, pp. 547-553.
10. C. Grecu et al, "Timing Analysis of Network on Chip Architectures for MP-SoC Platforms," Microelectronics J., vol. 36, no. 9, pp. 833-845.
11. http://www-flash.stanford.edu/apps/SPLASH/
12. http://rsim.cs.uiuc.edu/rsim/