3D chip stack technology using through-chip interconnects

IEEE Design and Test of Computers

Volumn 22, Issue 6, 2005, Pages 512-518

  Benkart, Peter ^a,b   Kaiser, Alexander ^b   Munding, Andreas ^b   Bschorr, Markus ^b   Pfleiderer, Hans Joerg ^b   Kohn, Erhard ^b   Heittmann, Arne ^a   Huebner, Holger ^a   Ramacher, Ulrich ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b UNIVERSITY OF ULM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER CIRCUITS; CRYSTAL GROWTH; ELECTROPLATING; EPITAXIAL GROWTH; ETCHING; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; METALLIZING; MICROPROCESSOR CHIPS; SCANNING ELECTRON MICROSCOPY; SOLDERING;

THREE DIMENSIONAL CHIP STACK TECHNOLOGY; THREE DIMENSIONAL FABRICATION PROCESS; THROUGH-CHIP INTERCONNECTS;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 28344456237     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2005.125     Document Type: Review

References (13)

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