Prediction router: Yet another low latency on-chip router architecture

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2009, Pages 367-378

  Matsutani, Hiroki ^a   Koibuchi, Michihiro ^b   Amano, Hideharu ^a   Yoshinaga, Tsutomu ^c  

^a KEIO UNIVERSITY   (Japan)

^b NATIONAL INSTITUTE OF INFORMATICS   (Japan)

^c UNIVERSITY OF ELECTRO COMMUNICATIONS   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; ECONOMIC AND SOCIAL EFFECTS; ENERGY UTILIZATION; FORECASTING; NETWORK ARCHITECTURE; NETWORK-ON-CHIP; PACKET SWITCHING;

APPLICATION PERFORMANCE; COMMUNICATION LATENCY; MANY-CORE ARCHITECTURE; NETWORK ENVIRONMENTS; NETWORK TOPOLOGY; PREDICTION ALGORITHMS; REAL APPLICATIONS; ROUTER ARCHITECTURE;

COMPUTER ARCHITECTURE;

EID: 64949183988     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2009.4798274     Document Type: Conference Paper

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