Last Level Cache (LLC) performance of data mining workloads on a CMP a case study of parallel bioinformatics workloads

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn 2006, Issue , 2006, Pages 88-98

  Jaleel, Aamer ^a   Mattina, Matthew ^b   Jacob, Bruce ^c  

^a INTEL CORPORATION   (United States)

^b Tilera Corp   (United States)

^c UNIVERSITY OF MARYLAND   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIOINFORMATICS WORKLOADS; CHIP-MULTIPROCESSORS (CMP); DATA SHARING; GENETIC DATA;

BUFFER STORAGE; DATA REDUCTION; HIERARCHICAL SYSTEMS; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; SILICON;

DATA MINING;

EID: 33748870740     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2006.1598115     Document Type: Conference Paper

References (33)

1. AMD MultiCore Technology: http://multicore.amd.com
2. The BioTeam: Infomatics Benchmarking Toolkit (IST), AMD Funded, http://bioteam.net/ibt/
3. HGBase: http://hgvbase.cgb.ki.se/
4. IBM Cell Processor: http://www-306.ibm.com/chips/techlib/techlib.nsf/ products/Cell
5. Intel Pentium Processor Extreme Edition: http://www.intel.com/products/ processor/pentiumXE/index.htm
6. PFam Database: http://www.sanger.ac.uk/Software/Pfam/
7. PIN home page: http://rogue.colorado.edu/Pin/.
8. SEMPHY Download Page: http://www.csuuji.ac.il/~nir/SEMPHY/
9. SPECOMP2001 http://www.spec.org/
10. "Sun Briefing In Computational Biology", White Paper, December, 2003.
11. G. A. Abandah, and E. S. Davidson. "Configuration Independent Analysis for Characterizing Shared-Memory Applications." In Proceedings of the 12th. International Parallel Processing Symposium (IPPS), Orlando, Florida, 1998.
12. G. A. Abandah. "Characterizing Shared-Memory Applications: A Case Study of the NAS Parallel Benchmarks." Technical Report, HPL-97-24, Hewlett Packard.
13. A. R. Alameldeen and D. A. Wood. "Variability in Architectural Simulations of Multi-threaded Workloads." In Proceedings of the 3rd International Conference on High Performance Computer Architecture (HPCA), Anaheim, California, 2003.
14. K. Albayraktaroglu, A. Jaleel, X. Wu, M. Franklin, B. Jacob, C. Tseng, and D. Yeung, "BioBench: A Benchmark Suite of Bioinformatics Applications." In the 5th International Symposium on Performance Analysis of Systems and Software (ISPASS), Austin, Texas, 2005.
15. L. A. Barroso, K. Gharachorloo, and E. Bugnion. "Memory System Characterization of Commercial Workloads." In Proceedings of the 25t International Symposium on Computer Architecture (ISCA), Barcelona, Spain, 1998.
16. Y. Chen, Q. Diao, C. Dulong, C. Lai, W. Hu, E. Li, W. Li, T. Wang, and Y. Zhang. "Performance Scalability of Data-Mining Workloads in Bioinformatics." Intel Technology Journal, Volume 09, Issue 02, May 19, 2005.
17. Y. Chen, Q. Diao, C. Dulong, C. Lai, W. Hu, E. Li, W. Li, T. Wang, and Y. Zhang. "Performance Scalability of Data-Mining Workloads in Bioinformatics." Technical Report.
18. Y. Cheng, J. Mark, C. Skawratananond, and T. K. Tzeng. "Scalability Comparison of Bioinformatics for Applications on AIX and Linux on IBM eServer pSeries 690." Redbooks Paper, August 2004.
19. Z. Chishti, M. Powell, and T. N. Vijaykumar. "Optimizing Replication, Communication, and Capacity Allocation in CMPs."In Proceedings of the 32nd International Symposium on Computer Architecture (ISCA), Wisconsin, Madison, 2005.
20. S. Chodnekar, V. Srinivasan, A. Vaidya, A. Sivasubramaniam, and C. Das. "Towards a Communication Characterization Methodology for Parallel Applications." In Proceedings of the 3rd International Conference on High Performance Computer Architecture (HPCA), San Antonio, Texas, 1997.
21. P. Dubey. "Recognition, Mining and Synthesis Moves Computers to the Era of Tera." Intel Technology Journal, February 2005.
22. N. Friedman, M. Ninio, I. Pe'er, and T. Pupko. "A Structural EM Algorithm for Phylogenetic Inference". In Journal of Computational Biology, 2001.
23. S. Goldschmidt and J. Hennessey. "The Accuracy of Trace-Driven Simulations of Multiprocessors." Tech Rep. CSL-TR92-546, Stanford University, Sept. 1992.
24. N. Friedman, M. Linial, I. Nachman, and D. Pe'er. "Using Bayesian Networks to Analyze Expression Data." Journal of Computational Biology, 7:601-620, 2000.
25. C. Liu, A. Sivasubramaniam, M. Kandemir. "Organizing the Last Line of Defense before Hitting the Memory Wall for CMPs." In Proceedings of the 6th International Conference on High Performance Computer Architecture (HPCA), Madrid, Spain, 2004.
26. E. Nurvitadhi, N. Chalainanont, and S. L. Lu. "Characterization of L3 Cache Behavior of SPECjAppServer2002 and TPC-C." In Proceedings of the 19th International Conference on Supercomputing (ICS), Boston, Massachusetts, 2005.
27. S. E. Perl and R. L. Sites. "Studies of Windows NT performance using dynamic execution traces." In Proceedings of the 2nd International Symposium on Operation Systems Design and Implementation (OSDI), Seattle, Washington, 1996.
28. V. Reddi, A. M.Settle, D. A. Connors and R. S. Cohn. "Pin: A Binary Instrumentation Tool for Computer Architecture Research and Education." In Proceedings of the Workshop on Computer Architecture Education, June 2004.
29. T. F. Smith and Michael S. Waterman. "Identification of Common Molecular Subsequences." In Proceedings of the Journal of Molecular Biology, 147:195-197, 1981.
30. E. Speight, H. Shafi, L. Zhang, R. Rajamony. "Adaptive Mechanisms and Policies for Managing Cache Hierarchies in CMPs." In Proceedings of the 32nd International Symposium on Computer Architecture (ISCA), Wisconsin, Madison, 2005.
31. A. Srivastava and A. Eustace, "ATOM: A System for Building Customized Program Analysis Tools", Programming Language Design and Implementation (PLDI), 1994, pp. 196-205.
32. S. Woo, M. Ohara, E. Torrie, J. Singh, and A. Gupta. "The SPLASH-2 Programs: Characterization and Methodology Considerations." In Proceedings of the 22nd International Symposium on Computer Architecture (ISCA), Santa Margherita Ligure, Italy, 1995.
33. M. Zhang and K. Asanovic. "Victim Replication: Maximizing capacity while Hiding Wire Delay in Tiled CMPs." In Proceedings of the 32nd International Symposium on Computer Architecture (ISCA), Wisconsin, Madison, 2005.