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Volumn , Issue , 2005, Pages 31-40

A nuca substrate for flexible CMP cache sharing

Author keywords

Cache sharing; Chip multiprocessor; Non uniform cache architecture

Indexed keywords

ENERGY UTILIZATION; PROGRAM PROCESSORS;

EID: 32844471317     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1088149.1088154     Document Type: Conference Paper
Times cited : (190)

References (24)
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    • Department of Computer Sciences, University of Texas at Austin, May
    • V. Agarwal, S. W. Keckler, and D. Burger. The effect of technology scaling on microarchitecture structures. Technical Report TR-00-02, Department of Computer Sciences, University of Texas at Austin, May 2001.
    • (2001) Technical Report TR-00-02
    • Agarwal, V.1    Keckler, S.W.2    Burger, D.3
  • 2
    • 0029308368 scopus 로고
    • Effective hardware-based data prefetching for high-performance processors
    • J.-L. Baer and T.-F. Chen. Effective hardware-based data prefetching for high-performance processors. IEEE Transactions on Computer, 44(5):609-623, 1995.
    • (1995) IEEE Transactions on Computer , vol.44 , Issue.5 , pp. 609-623
    • Baer, J.-L.1    Chen, T.-F.2
  • 10
    • 0025429331 scopus 로고
    • Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
    • N. P. Jouppi. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In Proceedings of the 17th annual international symposium on Computer Architecture, pages 364-373, 1990.
    • (1990) Proceedings of the 17th Annual International Symposium on Computer Architecture , pp. 364-373
    • Jouppi, N.P.1
  • 11
    • 3042669130 scopus 로고    scopus 로고
    • IBM Power5 Chip: A dual-core multithreaded processor
    • Mar/Apr
    • R. Kalla, B. Sinharoy, and J. M. Tendier. IBM Power5 Chip: A dual-core multithreaded processor. IEEE Micro, 24(2), Mar/Apr 2004.
    • IEEE Micro , vol.24 , Issue.2 , pp. 2004
    • Kalla, R.1    Sinharoy, B.2    Tendier, J.M.3
  • 18
    • 0003450887 scopus 로고    scopus 로고
    • Cacti 3.0: An integrated cache timing, power, and area model
    • HP, Western Research Laboratory
    • P. Shivakumar and N. P. Jouppi. Cacti 3.0: An integrated cache timing, power, and area model, Technical Report 2001-2, HP, Western Research Laboratory, 2001.
    • (2001) Technical Report 2001-2
    • Shivakumar, P.1    Jouppi, N.P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.