-
1
-
-
32844457663
-
The effect of technology scaling on microarchitecture structures
-
Department of Computer Sciences, University of Texas at Austin, May
-
V. Agarwal, S. W. Keckler, and D. Burger. The effect of technology scaling on microarchitecture structures. Technical Report TR-00-02, Department of Computer Sciences, University of Texas at Austin, May 2001.
-
(2001)
Technical Report TR-00-02
-
-
Agarwal, V.1
Keckler, S.W.2
Burger, D.3
-
2
-
-
0029308368
-
Effective hardware-based data prefetching for high-performance processors
-
J.-L. Baer and T.-F. Chen. Effective hardware-based data prefetching for high-performance processors. IEEE Transactions on Computer, 44(5):609-623, 1995.
-
(1995)
IEEE Transactions on Computer
, vol.44
, Issue.5
, pp. 609-623
-
-
Baer, J.-L.1
Chen, T.-F.2
-
3
-
-
0033722744
-
Piranha: A scalable architecture based on single-chip multiprocessing
-
June
-
L. A. Barroso, K. Gharachorloo, R. McNamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, and B. Verghese. Piranha: A scalable architecture based on single-chip multiprocessing. In The 27th Annual International Symposium on Computer Architecture, pages 282-293, June 2000.
-
(2000)
The 27th Annual International Symposium on Computer Architecture
, pp. 282-293
-
-
Barroso, L.A.1
Gharachorloo, K.2
McNamara, R.3
Nowatzyk, A.4
Qadeer, S.5
Sano, B.6
Smith, S.7
Stets, R.8
Verghese, B.9
-
6
-
-
27544432313
-
Optimizing replication, communication, and capacity allocation in cmps
-
Z. Chishti, M. D. Powell, and T. N. Vijaykumar. Optimizing replication, communication, and capacity allocation in cmps. In Proceedings of the 32nd annual international symposium on Computer Architecture, 2005.
-
(2005)
Proceedings of the 32nd Annual International Symposium on Computer Architecture
-
-
Chishti, Z.1
Powell, M.D.2
Vijaykumar, T.N.3
-
7
-
-
0033880036
-
The stanford hydra CMP
-
December
-
L. Hammond, B. A. Hubbert, M. Siu, M. K. Prabhu, M. Chen, and K. Olukotun. The Stanford Hydra CMP. IEEE Micro, pages 71-84, December 2000.
-
(2000)
IEEE Micro
, pp. 71-84
-
-
Hammond, L.1
Hubbert, B.A.2
Siu, M.3
Prabhu, M.K.4
Chen, M.5
Olukotun, K.6
-
10
-
-
0025429331
-
Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
-
N. P. Jouppi. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In Proceedings of the 17th annual international symposium on Computer Architecture, pages 364-373, 1990.
-
(1990)
Proceedings of the 17th Annual International Symposium on Computer Architecture
, pp. 364-373
-
-
Jouppi, N.P.1
-
11
-
-
3042669130
-
IBM Power5 Chip: A dual-core multithreaded processor
-
Mar/Apr
-
R. Kalla, B. Sinharoy, and J. M. Tendier. IBM Power5 Chip: A dual-core multithreaded processor. IEEE Micro, 24(2), Mar/Apr 2004.
-
IEEE Micro
, vol.24
, Issue.2
, pp. 2004
-
-
Kalla, R.1
Sinharoy, B.2
Tendier, J.M.3
-
12
-
-
0024668838
-
Inexpensive implementations of set-associativity
-
May
-
R. Kessler, R. Jooss, A. Lebeck, and M. Hill. Inexpensive implementations of set-associativity. In Proceedings of the 16th Annual International Symposium on Computer Architecture, pages 131-139, May 1989.
-
(1989)
Proceedings of the 16th Annual International Symposium on Computer Architecture
, pp. 131-139
-
-
Kessler, R.1
Jooss, R.2
Lebeck, A.3
Hill, M.4
-
13
-
-
0036949388
-
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
-
October
-
C. Kim, D. Burger, and S. W. Keckler. An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches. In Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 211-222, October 2002.
-
(2002)
Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)
, pp. 211-222
-
-
Kim, C.1
Burger, D.2
Keckler, S.W.3
-
18
-
-
0003450887
-
Cacti 3.0: An integrated cache timing, power, and area model
-
HP, Western Research Laboratory
-
P. Shivakumar and N. P. Jouppi. Cacti 3.0: An integrated cache timing, power, and area model, Technical Report 2001-2, HP, Western Research Laboratory, 2001.
-
(2001)
Technical Report 2001-2
-
-
Shivakumar, P.1
Jouppi, N.P.2
-
22
-
-
1642371317
-
Dynamic partitioning of shared cache memory
-
G. E. Suh, L. Rudolph, and S. Devadas. Dynamic partitioning of shared cache memory. Journal of Supercomputing, 28(1):7-26, 2004.
-
(2004)
Journal of Supercomputing
, vol.28
, Issue.1
, pp. 7-26
-
-
Suh, G.E.1
Rudolph, L.2
Devadas, S.3
-
23
-
-
0036298603
-
Power4 system microarchitecture
-
J. M. Tendler, S. Dodson, S. Fields, H. Le, and B. Sinharoy. Power4 system microarchitecture. IBM Journal of Research and Development, 46(1), 2002.
-
(2002)
IBM Journal of Research and Development
, vol.46
, Issue.1
-
-
Tendler, J.M.1
Dodson, S.2
Fields, S.3
Le, H.4
Sinharoy, B.5
-
24
-
-
0029179077
-
The splash-2 programs: Characterization and methodological considerations
-
S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The splash-2 programs: Characterization and methodological considerations. In Proceedings of the 22nd International Symposium on Computer Architecture, pages 24-36, 1995.
-
(1995)
Proceedings of the 22nd International Symposium on Computer Architecture
, pp. 24-36
-
-
Woo, S.C.1
Ohara, M.2
Torrie, E.3
Singh, J.P.4
Gupta, A.5
|