Architecting efficient interconnects for large caches with CACTI 6.0

IEEE Micro

Volumn 28, Issue 1, 2008, Pages 69-79

  Muralimanohar, Naveen ^a   Balasubramonian, Rajeev ^a,c   Jouppi, Norman P ^b  

^a UNIVERSITY OF UTAH   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

^c NONE   (United States)

Author keywords

Cache design; CACTI 6.0; On chip interconnects

Indexed keywords

COMPUTER ARCHITECTURE; INTERCONNECTION NETWORKS; PROGRAM PROCESSORS; RANDOM ACCESS STORAGE;

CACHE ACCESS; ON-CHIP INTERCONNECTS;

CACHE MEMORY;

EID: 41349122721     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2008.2     Document Type: Article

References (8)

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