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Volumn , Issue , 2002, Pages 418-419

Networks on chip: A new paradigm for systems on chip design

Author keywords

[No Author keywords available]

Indexed keywords

COMPONENT BASED DESIGN; NETWORKS ON CHIPS; ON CHIPS; PLUG-AND-PLAY; RELIABLE OPERATION; SYSTEMS ON CHIPS;

EID: 84893783336     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998307     Document Type: Conference Paper
Times cited : (287)

References (23)
  • 1
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chip: A new SoC paradigm
    • January
    • L. Benini and G. De Micheli, "Networks on Chip: A New SoC paradigm," IEEE Computer, January 2002.
    • (2002) IEEE Computer
    • Benini, L.1    De Micheli, G.2
  • 4
    • 0034848112 scopus 로고    scopus 로고
    • Route packets, not wires: On-chip interconnection networks
    • June
    • W. Dally, "Route packets, not wires: on-chip interconnection networks," DAC-Design Automation Conference, pp. 684-689, June 2001.
    • (2001) DAC-Design Automation Conference , pp. 684-689
    • Dally, W.1
  • 8
    • 0031999149 scopus 로고    scopus 로고
    • Electrical characteristics of interconnections for high-performance systems
    • February
    • A. Deutsch, "Electrical Characteristics of Interconnections for High-Performance Systems," Proceedings of the IEEE, vol. 86, no. 2, pp. 315-355, February 1998.
    • (1998) Proceedings of the IEEE , vol.86 , Issue.2 , pp. 315-355
    • Deutsch, A.1
  • 12
    • 0034245046 scopus 로고    scopus 로고
    • Toward achieving energy efficiency in presence of deep submicron noise
    • August
    • R. Hedge, N. Shanbhag, "Toward achieving energy efficiency in presence of deep submicron noise," IEEE Transactions on VLSI Systems, pp. 379-391, vol. 8, no. 4, August 2000.
    • (2000) IEEE Transactions on VLSI Systems , vol.8 , Issue.4 , pp. 379-391
    • Hedge, R.1    Shanbhag, N.2
  • 14
    • 0030285348 scopus 로고    scopus 로고
    • A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor
    • Nov.
    • J. Montanaro et al., "A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor," IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1703-1714, Nov. 1996.
    • (1996) IEEE Journal of Solid-State Circuits , vol.31 , Issue.11 , pp. 1703-1714
    • Montanaro, J.1
  • 16
    • 0032303326 scopus 로고    scopus 로고
    • On-chip bus structure for custom core logic design
    • W. Remaklus, "On-chip bus structure for custom core logic design," IEEE Wescon, pp. 7-14, 1998.
    • (1998) IEEE Wescon , pp. 7-14
    • Remaklus, W.1
  • 17
    • 0033903824 scopus 로고    scopus 로고
    • A global wiring paradigm for deep submicron design
    • February
    • D.Sylvester and K.Keutzer, "A Global Wiring Paradigm for Deep Submicron Design," IEEE Transactions on CAD/ICAS, Vol.19, No. 2, pp. 242-252, February 2000.
    • (2000) IEEE Transactions on CAD/ICAS , vol.19 , Issue.2 , pp. 242-252
    • Sylvester, D.1    Keutzer, K.2
  • 18
    • 0033689943 scopus 로고    scopus 로고
    • The future of Interconnection Technology
    • May
    • T. Theis, "The future of Interconnection Technology," IBM Journal of Research and Development, Vol. 44, No. 3, May 2000, pp. 379-390.
    • (2000) IBM Journal of Research and Development , vol.44 , Issue.3 , pp. 379-390
    • Theis, T.1
  • 23
    • 84893731885 scopus 로고    scopus 로고
    • http://public.itrs.net/


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.