-
1
-
-
0036149420
-
Networks on chip: A new SoC paradigm
-
January
-
L. Benini and G. De Micheli, "Networks on Chip: A New SoC paradigm," IEEE Computer, January 2002.
-
(2002)
IEEE Computer
-
-
Benini, L.1
De Micheli, G.2
-
3
-
-
33746995009
-
System-level power optimization: Techniques and tools
-
April
-
L. Benini, G. De Micheli, "System-Level Power Optimization: Techniques and Tools," ACM Transactions on Design Automation of Electronic Systems, vol. 5, no. 2, pp. 115-192, April 2000.
-
(2000)
ACM Transactions on Design Automation of Electronic Systems
, vol.5
, Issue.2
, pp. 115-192
-
-
Benini, L.1
De Micheli, G.2
-
4
-
-
0034848112
-
Route packets, not wires: On-chip interconnection networks
-
June
-
W. Dally, "Route packets, not wires: on-chip interconnection networks," DAC-Design Automation Conference, pp. 684-689, June 2001.
-
(2001)
DAC-Design Automation Conference
, pp. 684-689
-
-
Dally, W.1
-
6
-
-
0033314263
-
Soft error considerations for deep-submicron CMOS circuit applications
-
N. Cohen, T. Sriram, N. Leland, D. Moyer, S. Butler and R. Flatley, "Soft Error Considerations for Deep-Submicron CMOS Circuit Applications," IEDM, Proceedings of IEEE International Electron Device Meeting, pp. 315-318, 1999.
-
(1999)
IEDM, Proceedings of IEEE International Electron Device Meeting
, pp. 315-318
-
-
Cohen, N.1
Sriram, T.2
Leland, N.3
Moyer, D.4
Butler, S.5
Flatley, R.6
-
8
-
-
0031999149
-
Electrical characteristics of interconnections for high-performance systems
-
February
-
A. Deutsch, "Electrical Characteristics of Interconnections for High-Performance Systems," Proceedings of the IEEE, vol. 86, no. 2, pp. 315-355, February 1998.
-
(1998)
Proceedings of the IEEE
, vol.86
, Issue.2
, pp. 315-355
-
-
Deutsch, A.1
-
10
-
-
84893737717
-
Networks on silicon: Combining best effort and guaranteed service
-
K.Goossens, E. Rijpkema, P. Wielage, A. Peters and J. van Meerbergen, "Networks on Silicon: Combining Best Effort and Guaranteed Service," DATE-International Conference on Design and Test Europe, 2002.
-
(2002)
DATE-International Conference on Design and Test Europe
-
-
Goossens, K.1
Rijpkema, E.2
Wielage, P.3
Peters, A.4
Van Meerbergen, J.5
-
12
-
-
0034245046
-
Toward achieving energy efficiency in presence of deep submicron noise
-
August
-
R. Hedge, N. Shanbhag, "Toward achieving energy efficiency in presence of deep submicron noise," IEEE Transactions on VLSI Systems, pp. 379-391, vol. 8, no. 4, August 2000.
-
(2000)
IEEE Transactions on VLSI Systems
, vol.8
, Issue.4
, pp. 379-391
-
-
Hedge, R.1
Shanbhag, N.2
-
14
-
-
0030285348
-
A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor
-
Nov.
-
J. Montanaro et al., "A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor," IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1703-1714, Nov. 1996.
-
(1996)
IEEE Journal of Solid-State Circuits
, vol.31
, Issue.11
, pp. 1703-1714
-
-
Montanaro, J.1
-
15
-
-
0031373275
-
Power constrained design of multiprocessor interconnection networks
-
C. Patel, S. Chai, S. Yalamanchili, D. Shimmel, "Power constrained design of multiprocessor interconnection networks," IEEE International Conference on Computer Design, pp. 408-416, 1997.
-
(1997)
IEEE International Conference on Computer Design
, pp. 408-416
-
-
Patel, C.1
Chai, S.2
Yalamanchili, S.3
Shimmel, D.4
-
16
-
-
0032303326
-
On-chip bus structure for custom core logic design
-
W. Remaklus, "On-chip bus structure for custom core logic design," IEEE Wescon, pp. 7-14, 1998.
-
(1998)
IEEE Wescon
, pp. 7-14
-
-
Remaklus, W.1
-
17
-
-
0033903824
-
A global wiring paradigm for deep submicron design
-
February
-
D.Sylvester and K.Keutzer, "A Global Wiring Paradigm for Deep Submicron Design," IEEE Transactions on CAD/ICAS, Vol.19, No. 2, pp. 242-252, February 2000.
-
(2000)
IEEE Transactions on CAD/ICAS
, vol.19
, Issue.2
, pp. 242-252
-
-
Sylvester, D.1
Keutzer, K.2
-
18
-
-
0033689943
-
The future of Interconnection Technology
-
May
-
T. Theis, "The future of Interconnection Technology," IBM Journal of Research and Development, Vol. 44, No. 3, May 2000, pp. 379-390.
-
(2000)
IBM Journal of Research and Development
, vol.44
, Issue.3
, pp. 379-390
-
-
Theis, T.1
-
22
-
-
0034428335
-
DS-CDMA wired bus with simple interconnection topology for parallel processing system LSIs
-
Jan.
-
R. Yoshimura, T. Koat, S. Hatanaka, T. Matsuoka, K. Taniguchi, "DS-CDMA wired bus with simple interconnection topology for parallel processing system LSIs," IEEE Solid-State Circuits Conference, pp. 371-371, Jan. 2000.
-
(2000)
IEEE Solid-State Circuits Conference
, pp. 371-371
-
-
Yoshimura, R.1
Koat, T.2
Hatanaka, S.3
Matsuoka, T.4
Taniguchi, K.5
-
23
-
-
84893731885
-
-
http://public.itrs.net/
-
-
-
|