Low-voltage limitations of deep-sub-100-nm CMOS LSIs: View of memory designers

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2007, Pages 529-533

  Itoh, Kiyoo ^a   Yamaoka, Masanao ^a   Kawahara, Takayuki ^a  

^a HITACHI LTD   (Japan)

Author keywords

Bulk; Deep sub 100 nm CMOS LSIs; DRAM; FD SOI; Leakage; Logic gate; Minimum VDD; Speed variation; SRAM; VT variation

Indexed keywords

CMOS INTEGRATED CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; LEAKAGE CURRENTS; LOGIC GATES; NANOELECTRONICS; SILICON ON INSULATOR TECHNOLOGY; STATIC RANDOM ACCESS STORAGE;

LOW VOLTAGE LIMITATION; SPEED VARIATION; VT VARIATION;

LSI CIRCUITS;

EID: 34748842263     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1228784.1228789     Document Type: Conference Paper

References (19)

1. K. Itoh, VLSI Memory Chip Design, Springer-Verlag, 2001.
2. Y. Nakagome, IBM J. R&D, vol. 47, no. 5/6, pp. 525-552, 2003.
3. K. Itoh, ISCAS Dig., 2006.
4. R. Tsuchiya, IEDM Dig., pp. 631-634, 2004.
5. M. Yamaoka, Symp. VLSI Circuits Dig., pp. 288-291, 2004.
6. F. Assaderaghi, Symp. Low Power Electronics Dig., pp. 58-59, 1994.
7. G. Ono, ESSCIRC Dig., pp. 391-394, 2004.
8. R. Takemura, ISLPED Dig., pp. 123-126, 2006.
9. K. Hardee, ISSCC Dig., pp. 200-201, 2004.
10. W. K. Luk, Symp. VLSI Circuits Dig., pp. 228-229, 2006.
11. M. Khellah, ISSCC Dig., pp. 624-625, 2006.
12. M. Yamaoka, A-SSCC Dig., pp. 109-112, 2005.
13. K. Itoh, CICC Dig., pp. 339-344, 2004.
14. Balkaran S. Gill, Int. Test Conf. 2005.
15. N. Seifert, IEEE Trans. on Nuclear Science, pp. 3100-3106, vol. 49, No. 6, 2002.
16. H. Gotou, IEDM Dig. Tech. Papers, pp. 870-871, 1987.
17. K. Osada, ISSCC Dig., pp. 168-169, 2001.
18. K. Itoh, Int'l SOI Conf. Dig., pp. 103-104, Oct. 2006.
19. K. Itoh, Ultra-Low Voltage Nano-Scale Memories, Springer, to be published in 2007.