A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis

ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference

Volumn , Issue , 2008, Pages 286-289

  Yamaoka, Masanao ^a   Osada, Kenichi ^a   Kawahara, Takayuki ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVATION ANALYSIS; DYNAMIC ANALYSIS; LOGIC DESIGN;

ACTIVATION TIMES; BIAS CONTROLS; DYNAMIC STABILITY ANALYSES; LINE STRUCTURES; LOW VOLTAGES; OPERATING MARGINS; OPERATING STABILITIES; SRAM DESIGNS; SRAM MODULES; STABILITY ANALYSES; STABILITY IMPROVEMENTS;

STATIC RANDOM ACCESS STORAGE;

EID: 58049102639     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2008.4681848     Document Type: Conference Paper

References (8)

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