A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2008, Pages 22-23

  Truong, Dean ^a   Cheng, Wayne ^a   Mohsenin, Tinoosh ^a   Yu, Zhiyi ^a   Jacobson, Toney ^a   Landge, Gouri ^a   Meeuwsen, Michael ^a   Watnik, Christine ^a   Mejia, Paul ^a   Tran, Anh ^a   Webb, Jeremy ^a   Work, Eric ^a   Xiao, Zhibin ^a   Baas, Bevan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

DSP; DVFS; GALS; Many core

Indexed keywords

VLSI CIRCUITS;

CLOCK FREQUENCIES; COMPUTATIONAL PLATFORMS; CONFIGURABLE; DSP; DVFS; GALS; MANY-CORE; MULTIMEDIA WORKLOADS; PROGRAMMABLE PROCESSORS; SHARED MEMORIES; SUPPLY VOLTAGES;

TIMING CIRCUITS;

EID: 51949114723     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2008.4585936     Document Type: Conference Paper

References (8)

1. Z. Yu et al., "An Asynchronous Array of Simple Processors for DSP Applications," ISSCC 2006.
2. S. Vangal et al., "An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS," ISSCC 2007.
3. M. B. Taylor et al., "A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network", ISSCC 2003.
4. K. Agarwal and K. Nowka. "Dynamic power management by combination of dual static supply voltages". ISQED 2007.
5. M. Meeuwsen et al., "A Shared Memory Module for Asynchronous Array of Processors," EURASIP Journal on Embedded Systems, vol. 2007, Art. ID 86273.
6. R. Apperson et al., "A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains," IEEE TVLSI, Oct. 2007.
7. M. Tariq et al., "Development of an OFDM based High Speed Wireless LAN Platform using the TI C6x DSP," ICC 2002.
8. J. D. Bakker and F. C. Schoute, "LART: Design and implementation of an experimental wireless platform," Vehicular Tech. Conference 2000.