Fine-grain redundant logic using defect-prediction flip-flops

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 402-404

  Nakura, Toru ^a   Nose, Koichi ^a   Mizuno, Masayuki ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR CORRECTION; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING;

CHIP PRODUCTION; DEFECT PREDICTION; REDUNDANT LOGIC; SCAN CHAIN;

LOGIC CIRCUITS;

EID: 34548864074     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373464     Document Type: Conference Paper

References (2)

1. S. Das, D. Roberts, S. Lee, et al., "A Self-Tuning DVS Processor Using Delay-Error Detection and Correction," IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 792-804, Apr., 2006.
2. M. Nicolaidis, "Time Redundancy Based Soft-Error Tolerance to Resoue Nanometer Technologies," IEEE VLSI Test Symposium, pp. 86-94, Apr., 1999.