Reviews and future prospects of low-voltage embedded RAMs

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2004, Pages 339-344

  Itoh, Kiyoo ^a   Osada, Kenichi ^a   Kawahara, Takayuki ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; DYNAMIC RANDOM ACCESS STORAGE; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; MAGNETIC FIELDS; MAGNETIZATION; SIGNAL TO NOISE RATIO; STATIC RANDOM ACCESS STORAGE;

CIRCUIT DESIGN; GATE VOLTAGE; LEAKAGE-REDUCTION CIRCUITS; PERIPHERAL CIRCUITS;

RANDOM ACCESS STORAGE;

EID: 17044421681     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. Kiyoo Itoh, VLSI Memory Chip Design, Springer-Verlag, New York, 2001.
2. Y. Nakagome et al., "Review and prospects of low-voltage RAM circuits," IBM J. R & D, vol. 47, no. 5/6, pp. 525-552, Sep./Nov. 2003.
3. T. Kamei et al., "A Resume-Standby Application Processor for 3G Cellular Phones," 2004 ISSCC Dig. Tech. Papers, pp. 336-337, Feb. 2004.
4. M. Yamaoka et al., "A 300 MHz 25μA/Mb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Mode for Mobile-Phone Application Processor," 2004 ISSCC Dig. Tech. Papers, pp. 494-495, Feb. 2004.
5. K. Hardee et at., "A 0.6V 205MHz 19.5ns tRC 16Mb Embedded DRAM," 2004 ISSCC Dig. Tech. Papers, pp. 494-495, Feb. 2004.
6. F. Morishita et al., "A 312MHz 16Mb Random-Cycle Embedded DRAM Macro with 73 μW Power-Down Mode for Mobile Applications," 2004 ISSCC Dig. Tech. Papers, pp. 202-203, Feb. 2004.
7. M. Yamaoka et al., "Low Power SRAM Menu for SOC Application Using Yin-Yang-Feedback Memory Cell Technology," Symp. VLSI Circuits Dig., June 2004.
8. K. Nii et al., "A 90 nm Low Power 32K-Byte Embedded SRAM with Gate Leakage Suppression Circuit for Mobile Applications," Symp. VLSI Circuits Dig., pp. 247-150, June 2003.
9. T. Inukai and T. Hiramoto, "Suppression of Stand-by Tunnel Current in Ultra-Thin Gate Oxide MOSFETs by Dual Oxide Thickness MTCMOS (DOT-MTCMOS)," Ext. Abst. 1999 lnt'l Conf. SSDM, Tokyo, pp. 264-265, 1999.
10. K. Osada et al., "16.7fA/cell Tunnel-Leakage-Suppressed 16Mb SRAM for Handling Cosmic-Ray-Induced Multi-Errors," 2003 ISSCC Dig. Tech. Papers, pp. 302-303, Feb. 2003.
11. H. Noda et al., "A 143MHz 1.1W 4.5Mb Dynamic TCAM with Hierarchical Searching and Shift Redundancy Architecture," 2004 ISSCC Dig. Tech. Papers, pp. 208-209, Feb. 2004.
12. J. Nahas et al., "A 4Mb 0.18μm 1T1MTJ Toggle MRAM Memory," 2004 ISSCC Dig. Tech. Papers, pp. 44-45, Feb. 2004.
13. W. Y. Cho et al., "A 0.18μm 3.0V 64Mb Non-Volatile Phase-Transition Random-Access Memory(PRAM)," 2004 ISSCC Dig. Tech. Papers, pp. 40-41, Feb. 2004.
14. Y. Nakagome et al., "Sub-l-V swing bus architecture for future low-power ULSIs," Symp. VLSI Circuits Dig., pp. 82-83, June 1992.
15. T. Kawahara et al., "Subthreshold current reduction for decoded-driver by self-reverse biasing," IEEE J. Solid-State Circuits, vol. 28, pp. 1136-1144, Nov. 1993.
16. M. Horiguchi et al., "Switched-source-irnpedance CMOS circuit for low standby subthreshold current giga-scale LSI'/s," IEEE J. Solid-State Circuits, vol. 28, pp. 1131-1135, Nov. 1993.
17. T. Sakata et al., "Subthreshold-current reduction circuits for multi-gigabit DRAMs," IEEE J. Solid-State Circuits, vol. 29, pp. 761-769, July 1994.
18. K. Osada et al., "Universal-Vdd 0.65-2.0V 32 kB Cache using Voltage-Adapted Timing-Generation Scheme and a Lithographical-Symmetric Cell," 2001 ISSCC, Dig. Tech. Papers, pp. 168-169, Feb. 2001.