Statistical characterization and on-chip measurement methods for local random variability of a process using sense-amplifier-based test structure

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 400-402

  Mukhopadhyay, Saibal ^a   Kim, Keunwoo ^a   Jenkins, Keith A ^a   Chuang, Ching Te ^a   Roy, Kaushik ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); BUILT-IN SELF TEST; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT TESTING; VOLTAGE MEASUREMENT;

ON CHIP DIGITAL CHARACTERIZATION; RANDOM VARIATION; TEST CIRCUITS;

CHIP SCALE PACKAGES;

EID: 34548835200     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373463     Document Type: Conference Paper

References (6)

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2. H. Klimach, A. Arnaud, M.C. Schneider and C.-Calup-Montoro, "Characterization of MOS Transistor Current Mismatch," Symp. Integrated Circuits Sys. Design, pp. 33-38, Sep., 2004.
3. K. Agarwal, F. Liu, C. McDoweel, et al., "A Test Structure for Characterizing Local Device Mismatches," Symp. VLSI Circuits, pp. 67, Jun., 2006.
4. B. Wicht, T. Nirschl and D. Schmitt-Landsiedel, "Yield and Speed Optimization of A Latch-Type Voltage Sense Amplifier," IEEE J. Sold-State Circuits, vol. 39, no. 7, pp. 1148-1158, Jul., 2004.
5. Berkeley Predictive Technology Model (BPTM): http://www-device.eecs. berkeley.edu/~ptm/.
6. Y. Taur and T.K. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 1998.