Low-Vt small-offset gated preamplifier for sub-1V DRAM arrays gigabit

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 142-144

  Akiyama, Satoru ^a   Sekiguchi, Tomonori ^a   Takemura, Riichiro ^a   Kotabe, Akira ^a   Itoh, Kiyoa ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349291222     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977348     Document Type: Conference Paper

References (5)

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3. S. Mukhopadhyay, K. Kim, K.A. Jenkins, et al., "Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure", ISSCC Dig. Tech. Papers, pp. 400-401, Feb. 2007.
4. K. Itoh, M. Horiguchi, M. Yamaoka, "Low-Voltage Limitations of Memory-Rich Nano-Scale CMOS LSIs", ESSCIRC Dig. Tech. Papers, pp. 68-75, Sept. 2007.
5. K. Itoh and R. Takemura, "Low-Voltage Limitation of Nano-Scale CMOS LSIs: Current Status and Future Trends", EDSSC Dig. Tech. Papers, pp. 83-86, Dec. 2007