Low power data holding circuit with an intermittent power supply scheme for sub-1V MT-CMOS LSIs

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1996, Pages 14-15

  Akamatsu, Hironori ^a   Iwata, Toru ^a   Yamamoto, Hiro ^a   Hirata, Takashi ^a   Yamauchi, Hiroyuki ^a   Kotani, Hisakazu ^a   Matsuzawa, Akira ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT MANUFACTURE; LEAKAGE CURRENTS; LOGIC CIRCUITS; LSI CIRCUITS; RANDOM ACCESS STORAGE; TRANSISTORS;

BULK SOURCE VOLTAGE; DATA HOLDING CIRCUIT; DATA LATCH CIRCUIT; DRAIN SOURCE VOLTAGE; GATE SOURCE VOLTAGE; INTERMITTENT POWER SUPPLY; THRESHOLD VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 0029715111     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)