A 153Mb-SRAM design will dynamic stability enhancement and leakage reduction in 45nm high-κ metal-gate CMOS technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 376-378

  Hamzaoglu, Fatih ^a   Zhang, Kevin ^a   Wang, Yih ^a   Ahn, Hong Jo ^a   Bhattacharya, Uddalak ^a   Chen, Zhanping ^a   Ng, Yong Gee ^a   Pavlov, Andrei ^a   Smits, Ken ^a   Bohr, Mark ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LOGIC DESIGN; STATIC RANDOM ACCESS STORAGE;

ACTIVE FEEDBACK CONTROL; BUILDING BLOCKES; CMOS TECHNOLOGY; FORWARD BODY BIAS; LEAKAGE REDUCTION; PVT VARIATIONS; STABILITY ENHANCEMENT; VOLTAGE GENERATORS;

INTEGRATED CIRCUIT DESIGN;

EID: 49549092261     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523214     Document Type: Conference Paper

References (6)

1. K. Mistry, et al., "A 45nm Logic Technology with higk-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging," IEDM Tech. Dig., 2007.
2. K. Zhang, U. Bhattacharya, C. Zhanping et al., "SRAM design on 65-nm CMOS Technology with Dynamic Sleep Transistor for Leakage Reduction," IEEE J. Solid-State Circuits, vol.40, pp. 895-901, April 2005.
3. V. George, "Penryn: 45-nm Next Generation Intel® Core™ 2 Processor," ASSOC Dig. Tech. Papers, Nov. 2007.
4. M. Miyazaki, G. Ono and K. Ishibashi, "A 1000-MIPS/W Microprocessor Using Speed-Adaptive Threshold-Volt age CMOS with Forward Bias," ISSCC Dig. Tech. Papers, pp. 420-421, 475, Feb. 2000.
5. K.-S. Min, K. Kanda and T. Sakurai, "Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's," in Symp. Low Power Electronics and Design, pp. 66-71, Aug. 2003.
6. M. Khellah, D. Somasekhar, Y. Ye et al., "A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process with Actively Clamped Sleep Transistor," IEEE J. Solid-State Circuits, vol.42, pp. 233-242, Jan. 2007.